Granted Patent B2

US 8,949,551 · App. 13/249,829 · Granted Feb 3, 2015

Abstract

Claims (61)

1. A data processing system comprising:

a memory protection unit (MPU);

a plurality of region descriptors associated with the MPU, wherein each region descriptor is associated with one of multiple subsets of the region descriptors and includes an address range, protection settings, and attributes for a respective region of memory, the subsets including a subset of data-only region descriptors, a subset of instruction-only region descriptors, and a subset of shared region descriptors;

a first shared region descriptor of the subset of shared region descriptors, the first shared region descriptor including a first indicator to selectively configure the first shared region descriptor to operate as one of a data region descriptor or an instruction region descriptor;

first instruction compare logic coupled to an instruction address bus and to the first shared region descriptor, the first instruction compare logic to compare an address at the instruction address bus with a first address range specified at the first region descriptor; and

first data compare logic coupled to a data address bus and to the first shared region descriptor, the first data compare logic to compare an address at the data address bus with the first address range;

wherein the first instruction compare logic is enabled and the first data compare logic is disabled if the first indicator is in a first state; and

wherein the first instruction compare logic is disabled and the first data compare logic is enabled if the first indicator is in a second state.

2. The data processing system of claim 1 further comprising:

MPU control logic operable to perform memory protection functions for instructions using the instruction-only region descriptors.

3. The data processing system of claim 1 further comprising:

MPU control logic operable to perform memory protection functions for data using the data-only region descriptors.

4. The data processing system of claim 1 further comprising:

MPU control logic operable to perform memory protection functions for data and instructions using the shared region descriptors.

5. The data processing system of claim 1 further comprising:

a MPU configuration register including information regarding the number of data-only region descriptors, instruction-only region descriptors, and shared region descriptors.

6. The data processing system of claim 1 further comprising:

a MPU assist register including an instruction entry that indicates whether a MPU region descriptor is one of the data-only region descriptors or one of the instruction-only region descriptors.

7. The data processing system of claim 1 further comprising:

a MPU assist register including a shared entry select that controls use of the shared region descriptors.

8. The data processing system of claim 1 further comprising:

a MPU assist register including an entry select indicator that is used to select one of the shared region descriptors.

9. The data processing system of claim 1 further comprising:

control logic operable to number individual entries within each of the subsets of the region descriptors starting at entry zero in each subset.

10. A data processing system comprising:

a memory protect unit (MPU) including:

a set of instruction region descriptors to selectively allow or deny instruction access requests;

first instruction compare logic to control access to a memory for the instruction access requests;

a set of data region descriptors to selectively allow or deny data access requests;

first data compare logic to control access to the memory for the data access requests;

a set of shared region descriptors, wherein each shared region descriptor is selectively configurable to operate as one of a data region descriptor or an instruction region descriptor, the set of shared region descriptors including a first shared region descriptor, the first shared region descriptor including a first indicator to selectively configure the first shared region descriptor to operate as one of a data region descriptor or an instruction region descriptor;

second instruction compare logic coupled to an instruction address bus and to the first shared region descriptor, the first instruction compare logic to compare an address at the instruction address bus with a first address range specified at the first region descriptor; and

second data compare logic coupled to a data address bus and to the first shared region descriptor, the first data compare logic to compare an address at the data address bus with the first address range;

wherein the second instruction compare logic is enabled and the second data compare logic is disabled if the first indicator is in a first state; and

wherein the second instruction compare logic is disabled and the second data compare logic is enabled if the first indicator is in a second state.

11. The data processing system of claim 10 further comprising:

a MPU configuration register that specifies quantities of the instruction region descriptors, data region descriptors, and shared region descriptors.

12. The data processing system of claim 11 further comprising:

supervisor execute indicators and user execute indicators included only in the instruction region descriptors and the shared region descriptors.

13. The data processing system of claim 10 further comprising:

user read/write permission indicators and supervisor read/write permission indicators included only in the data region descriptors and the shared region descriptors.

14. The data processing system of claim 10 further comprising:

MPU control logic;

a MPU assist register including indicators that enable the MPU control logic to determine whether to use one of the instruction region descriptors, one of the data region descriptors, or one of the shared region descriptors for an operation on a region descriptor.

15. The data processing system of claim 10 further comprising:

MPU control logic; and

a MPU assist register including an indicator that enables the MPU control logic to determine whether to use one of the shared region descriptors for an operation on a region descriptor.

16. A method comprising:

determining whether a shared indicator included at an assist register of a memory protection unit (MPU) is in a first state, the assist register for updating region descriptors of the MPU;

if the shared indicator is in the first state, selecting an entry in a set of shared region descriptors in the MPU of a data processing system for access, wherein a shared region descriptor is selectively configurable to operate as one of a data region descriptor or an instruction region descriptor based on an indicator included at the region descriptor;

determining whether the shared indicator is in a second state; and

if the shared indicator is in the second state, selecting an entry in a set of data region descriptors or a set of instruction region descriptors in the MPU for access, and disabling selection of an entry in the set of shared region descriptors for access.

17. The method of claim 16 further comprising:

determining quantities of the instruction region descriptors, the data region descriptors, and the shared region descriptors based on information in a MPU configuration register.

18. The method of claim 17 further comprising:

if the shared indicator is in the second state, determining whether an instruction indicator is in a first instruction state; and

if the instruction indicator is in the first instruction state, selecting an entry in the instruction region descriptors for access.

19. The method of claim 18 further comprising:

if the instruction indicator is not in the first instruction state, selecting an entry in the data region descriptors for access.

20. The method of claim 16 further comprising:

selecting an entry in the shared region descriptors, instruction region descriptors, or data region descriptors using an entry select indicator in the MPU assist register.

Assignments (32)