IP Library Granted Patent US 8,390,091
Granted Patent B2
US 8,390,091 · App. 13/143,548 · Granted Mar 5, 2013

Semiconductor structure, an integrated circuit including a semiconductor structure and a method for manufacturing a semiconductor structure

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Quick Facts
Patent No.
US 8,390,091
App. No.
13/143,548
Granted
Mar 5, 2013
Kind
B2
Abstract

A monolithic semiconductor structure includes a stack of layers. The stack includes a substrate; a first layer made from a first semiconductor material; and a second layer made from a second semiconductor material. The first layer is situated between the substrate and the second layer and at least one of the first semiconductor material and the second semiconductor material contains a III-nitride material. The structure includes a power transistor, including a body formed in the stack of layers; a first power terminal at a side of the first layer facing the second layer; a second power terminal at least partly formed in the substrate; and a gate structure for controlling the propagation through the body of electric signals between the first power terminal and the second power terminal. The structure further includes a vertical Schottky diode, including: an anode; a cathode including the substrate, and a Schottky barrier between the cathode and the anode, the Schottky barrier being situated between the substrate and a anode layer in the stack of layers.

Claims (44)

1. A monolithic semiconductor structure, including;

a stack of layers including:

a substrate;

a first layer made from a first semiconductor material; and

a second layer made from a second semiconductor material, said first layer being situated between the substrate and the second layer and at least one of said first semiconductor material and said second semiconductor material containing a III-nitride material;

said structure including a power transistor, including:

a body formed in said stack of layers;

a first power terminal at a side of said first layer facing said second layer;

a second power terminal at least partly formed in said substrate; and

a gate structure for controlling the propagation through said body of electric signals between said first power terminal and said second power terminal; and

said structure further including a Schottky diode, including:

an anode;

a cathode including said substrate; and

a Schottky barrier between said cathode and said anode, said Schottky barrier being situated between said substrate and an anode layer in the stack of layers.

2. A monolithic semiconductor structure as claimed in claim 1 , including a conducting path between the anode and said first power source.

3. A monolithic semiconductor structure as claimed in claim 1 , including a recess through the first layer and/or the second layer and wherein said cathode is at least partially formed by a part of said recess filled with a cathode semiconductor material.

4. A monolithic semiconductor structure as claimed in claim 3 , wherein said first semiconductor material is an epitaxial material and said recess is filled with an epitaxial regrowth material.

5. A monolithic semiconductor structure as claimed in claim 3 , wherein said recess extends from a substrate side of said first layer through the first layer and the second layer, and wherein said recess is filled with a cathode III-nitride material.

6. A monolithic semiconductor structure as claimed in claim 1 , wherein said cathode III-nitride material is doped GaN.

7. A monolithic semiconductor structure as claimed in claim 5 , wherein said cathode III-nitride material has a higher doping concentration in a part of the recess adjacent to the substrate side than in a part of the recess adjacent to the anode.

8. A monolithic semiconductor structure as claimed in claim 1 , including an insulating region between said Schottky diode and said body which electrically separates an aread in which said Schottky diode is situated from said body.

9. A monolithic semiconductor structure as claimed in claim 1 , wherein said substrate is Ohmic.

10. A monolithic semiconductor structure as claimed in claim 1 , wherein said field effect transistor is a hetero-structure field effect transistor and said body includes a hetero-junction structure between said first power terminal and said second power terminal, said hetero-junction structure including an interface at which said first layer and said second layer are in contact with each other and along which interface, when in operation, a two dimensional electron gas is formed.

11. A monolithic semiconductor structure as claimed in claim 1 , wherein said first semiconductor material has a different band-gap than said second semiconductor material.

12. A monolithic semiconductor structure as claimed in claim 1 , including at least one intermediate layer, such as a transition layer and/or a nucleation layer, between the first layer and the substrate.

13. A monolithic semiconductor structure as claimed in claim 1 , wherein said first semiconductor and/or said second semiconductor material are a III-nitride material selected from the group consisting of: III-nitride material, binary III-nitride material, ternary III-nitride material, quaternary III-nitride material, GaN, AlGaN, InGaN; AlInN.

14. A monolithic semiconductor structure as claimed in claim 1 , wherein said first semiconductor material is not intentionally doped GaN and/said second semiconductor material is a material containing AlGaN.

15. A monolithic semiconductor structure as claimed in claim 1 , wherein said first layer has a thickness of at least 5 micrometers, such as 6 micrometers.

16. A monolithic semiconductor structure as claimed in claim 1 , wherein said substrate semiconductor material includes one or more materials of the group consisting of: SiC, doped or undoped Si, epitaxial grown material, crystalline material, poly-crystalline material.

17. An integrated circuit including at least one monolithic semiconductor structure as claimed in claim 1 and additional electronic components connected to the monolithic semiconductor structure to form an electronic circuit.

18. A method for manufacturing a monolithic semiconductor structure, including:

providing a stack of layers including:

a substrate;

a first layer made from a first semiconductor material; and

a second layer made from a second semiconductor material, said first layer being situated between the substrate and the second layer and at least one of said first semiconductor material and said second semiconductor material containing a III-nitride material; and

providing a power transistor, including:

forming a body in said stack of layers;

forming a first power terminal at a side of said first layer facing said second layer;

forming a second power terminal in said substrate;

forming a gate structure for controlling the propagation through said body of electric signals between said first power terminal and said second power terminal; and

providing a vertical Schottky diode, including:

forming an anode;

forming a cathode including said substrate; and

forming a Schottky barrier between said cathode and said anode, said Schottky barrier being situated between said substrate and an anode layer in said stack of layers.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2011
From: RENAUD, PHILIPPE
To: FREESCALE SEMICONDUCTOR INC
Reel/Frame 026552/0867 →