IP Library Granted Patent US 9,035,629
Granted Patent B2
US 9,035,629 · App. 13/097,411 · Granted May 19, 2015

Voltage regulator with different inverting gain stages

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Quick Facts
Patent No.
US 9,035,629
App. No.
13/097,411
Granted
May 19, 2015
Kind
B2
Abstract

A voltage regulator includes a regulating transistor and a control circuit. The regulating transistor has a first current electrode for providing a regulated voltage, a second current electrode, and a control electrode. The control circuit has an output coupled to the control electrode of the regulating transistor, and an input coupled to the first current electrode of the regulating transistor. The control circuit includes a first inverting gain stage having a first load element, and a second inverting gain stage having a second load element. One of the first or second load elements is characterized as being a diode and the other of the first or second load elements is biased by a bias circuit.

Claims (52)

1. A voltage regulator comprising:

a regulating transistor having a first current electrode for providing a regulated voltage, a second current electrode, and a control electrode; and

a control circuit having an output coupled to the control electrode of the regulating transistor, and an input coupled to the first current electrode of the regulating transistor, the control circuit comprising a first inverting gain stage having a first load element, and a second inverting gain stage having a second load element, wherein one of the first load element or the second load element is characterized as being a diode and the other of the first load element or the second load element is biased by a bias circuit, wherein one of the first inverting gain stage or the second inverting gain stage includes an input transistor that includes a control electrode coupled to the first current electrode of the regulating transistor, wherein the regulating transistor and the input transistor are of a same channel conductivity type;

wherein the bias circuit comprises:

a first transistor having a first current electrode coupled to a first power supply voltage terminal, a second current electrode and a control electrode both coupled together, and

a second transistor having a first current electrode and a control electrode both coupled to the second current electrode and the control electrode of the first transistor, and a second current electrode coupled to a second power supply voltage terminal.

2. The voltage regulator of claim 1 , wherein the first inverting gain stage further comprises the input transistor, the input transistor has a first current electrode coupled to a first terminal of the first load element and a second current electrode coupled to a power supply voltage terminal.

3. The voltage regulator of claim 1 , wherein the second inverting gain stage further comprises a first transistor having a first current electrode coupled to a first terminal of the second load element, a second current electrode coupled to a first power supply voltage terminal, and a control electrode coupled to an output terminal of the first inverting gain stage.

4. The voltage regulator of claim 1 , wherein the second load element comprises a third transistor having a first current electrode coupled to the first power supply voltage terminal, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode coupled to the control electrode of the regulating transistor.

5. The voltage regulator of claim 1 , wherein the first load element comprises a first transistor having a first current electrode coupled to a first power supply voltage terminal, and a second current electrode and a control electrode coupled together.

6. The voltage regulator of claim 1 , wherein the first load element of the first inverting gain stage comprises a diode, the first inverting gain stage has an input coupled to the first current electrode of the regulating transistor, and the first inverting gain stage has an output, and wherein the second load element is biased by the bias circuit, the second inverting gain stage has an input coupled to the output of the first inverting gain stage, and the second inverting gain stage has an output coupled to the control electrode of the regulating transistor.

7. The voltage regulator of claim 1 , wherein the first load element comprises a third transistor having a first current electrode coupled to a first power supply voltage terminal, a second current electrode coupled to an input of the second inverting gain stage, and a control electrode coupled to the bias circuit in a current mirror configuration.

8. The voltage regulator of claim 1 , wherein the diode is further characterized as being a diode-connected transistor.

9. A voltage regulator comprising:

a regulating transistor having a first current electrode for providing a regulated voltage, a second current electrode, and a control electrode; and

a control circuit having an output coupled to the control electrode of the regulating transistor, and an input coupled to the first current electrode of the regulating transistor, the control circuit comprising a first inverting gain stage having a first load element, and a second inverting gain stage having a second load element, wherein one of the first load element or the second load element is characterized as being a diode and the other of the first load element or the second load element is biased by a bias circuit;

wherein the first load element of the first inverting gain stage is biased by the bias circuit, the first inverting gain stage has an input coupled to the first current electrode of the regulating transistor, and the first inverting gain stage as an output, and wherein the second load element includes a diode, the second inverting gain stage has an input coupled to the output of the first inverting gain stage, and the second inverting gain stage has an output coupled to the control electrode of the regulating transistor.

10. The voltage regulator of claim 9 , wherein the bias circuit comprises:

a first transistor having a first current electrode coupled to a first power supply voltage terminal, a second current electrode and a control electrode both coupled together, and

a second transistor having a first current electrode and a control electrode both coupled to the second current electrode and the control electrode of the first transistor, and a second current electrode coupled to a second power supply voltage terminal.

11. A voltage regulator comprising:

a regulating transistor having a first current electrode for providing a regulated voltage, a second current electrode, and a control electrode;

a first inverting gain stage comprising:

a first transistor having a first current electrode, a control electrode and a second current electrode coupled together; and

a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the first current electrode of the regulating transistor, and a second current electrode;

a second inverting gain stage comprising:

a third transistor having a first current electrode, a control electrode, and a second current electrode coupled to the control electrode of the regulating transistor; and

a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode; and

a bias circuit coupled to provide a bias voltage to the control electrode of the third transistor;

wherein the regulating transistor and the second transistor are of a first channel conductivity type and the first transistor is of a second channel conductivity type opposite the first channel conductivity type.

12. The voltage regulator of claim 11 , wherein the bias circuit comprises:

a fifth transistor having a first current electrode coupled to a first power supply voltage terminal, a second current electrode and a control electrode both coupled together and to the control electrode of the third transistor; and

a sixth transistor having a first current electrode and a control electrode both coupled to the second current electrode and the control electrode of the fifth transistor, and a second current electrode coupled to a second power supply voltage terminal.

13. The voltage regulator of claim 11 , further comprising an enabling transistor coupled in parallel with the regulating transistor, the enabling transistor responsive to an enable signal for enabling and disabling the voltage regulator.

14. The voltage regulator of claim 11 , wherein the first current electrode of the regulating transistor is coupled to provide the regulated voltage to a memory array.

15. The voltage regulator of claim 11 , wherein the regulating transistor, the second transistor, and the fourth transistor are N-channel transistors and the first transistor and the third transistor are P-channel transistors.

16. The voltage regulator of claim 11 wherein the second current electrode of the second transistor and the second current electrode of the fourth transistor are each coupled to a first power supply terminal.

17. A voltage regulator comprising:

a regulating transistor having a first current electrode for providing a regulated voltage, a second current electrode, and a control electrode;

a first inverting gain stage comprising:

a first transistor having a first current electrode, a control electrode, and a second current electrode; and

a second transistor having a first current electrode coupled to the second current electrode of the first transistor, a control electrode coupled to the first current electrode of the regulating transistor, and a second current electrode;

a second inverting gain stage comprising:

a third transistor having a first current electrode, and a second current electrode and a control electrode coupled together and to the control electrode of the regulating transistor; and

a fourth transistor having a first current electrode coupled to the second current electrode of the third transistor, a control electrode coupled to the second current electrode of the first transistor, and a second current electrode; and

a bias circuit coupled to provide a bias voltage to the control electrode of the first transistor.

18. The voltage regulator of claim 17 , wherein the bias circuit forms a current mirror with the first transistor.

19. The voltage regulator of claim 17 , wherein the regulating transistor, the second transistor and the fourth transistor are N-channel transistors, and the first transistor and the third transistor are P-channel transistors.

20. The voltage regulator of claim 17 , further comprising an enabling transistor coupled in parallel with the regulating transistor, the enabling transistor responsive to an enable signal for enabling and disabling the voltage regulator.

21. The voltage regulator of claim 17 , wherein the bias circuit comprises:

a fifth transistor having a first current electrode coupled to a first power supply voltage terminal, and a second current electrode and control electrode coupled together; and

a sixth transistor having a first current electrode and control electrode coupled together, and a second current electrode coupled to a second power supply voltage terminal.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
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To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
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PATENT RELEASE Recorded Dec 21, 2015
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SECURITY AGREEMENT Recorded Nov 6, 2013
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