MOS transistor drain-to-gate leakage protection circuit and method therefor
View Patent ↗A circuit having an active mode and a sleep mode includes a power transistor, an amplifier, and a protection circuit. The power transistor has a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the circuit for coupling to a load, and a control electrode, wherein the power transistor is characterized by having a threshold voltage and a leakage current, wherein the leakage current occurs between the control electrode and the first current electrode during the sleep mode. The amplifier has an output coupled to the control electrode of the power transistor that provides an active output during the active mode. The protection circuit detects the leakage current and prevents the leakage current from developing a voltage on the control electrode of the power transistor that exceeds the threshold voltage of the power transistor.
1. A first circuit having an active mode and a sleep mode, comprising:
a power transistor having a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the first circuit for coupling to a load, and a control electrode, wherein the power transistor is characterized by having a threshold voltage and a leakage current, wherein the leakage current occurs between the control electrode and the first current electrode during the sleep mode;
an amplifier having an output coupled to the control electrode of the power transistor that provides an active output during the active mode; and
a protection circuit coupled to the control electrode of the power transistor, wherein the protection circuit detects the leakage current and prevents the leakage current from developing a first voltage on the control electrode of the power transistor that exceeds the threshold voltage of the power transistor, wherein the protection circuit prevents the leakage current from developing the first voltage by providing a current path to pull down a voltage on the control electrode of the power transistor.
2. The first circuit of claim 1 , wherein the protection circuit comprises:
a current mirror circuit coupled to the first power supply terminal having a first input coupled to the control electrode of the power transistor and having a second input coupled to receive a sleep signal.
3. The first circuit of claim 2 , wherein the second input is coupled to the sleep signal through a buffer circuit.
4. The first circuit of claim of 3 wherein the buffer circuit comprises:
a first transistor having a control electrode coupled to the sleep signal, a first current electrode coupled to the power supply terminal, and a second current electrode; and
a resistance having a first terminal coupled to the second current electrode of the first transistor and a second terminal coupled to a second power supply terminal.
5. The first circuit of claim 2 , wherein the current minor has an output, the protection circuit further comprising a first transistor having a first current electrode coupled to the gate of the power transistor, a control electrode coupled to the output of the current mirror, and a second current electrode coupled to the output of the first circuit.
6. The first circuit of claim 1 , wherein the amplifier comprises:
a first N channel transistor having a control electrode for receiving an input signal, a drain coupled to the control electrode of the power transistor; a source coupled to the output of the first circuit, and a body connected to the output of the first circuit; and
a first P channel transistor having a control electrode for receiving the input signal, a drain coupled to the control electrode of the power transistor; a source coupled to a boosted voltage having a voltage level that is above a voltage level at the first power supply terminal, and a body connected to the boosted voltage.
7. A first circuit having an active mode and a sleep mode, comprising:
a power transistor having a first current electrode coupled to a first power supply terminal, a second current electrode as an output of the first circuit for coupling to a load, and a first control electrode, wherein the power transistor is characterized by having a threshold voltage and a leakage current, wherein the leakage current occurs between the first control electrode and the first current electrode during the sleep mode;
an amplifier having an output coupled to the first control electrode of the power transistor that provides an active output during the active mode; and
a protection circuit that detects the leakage current and prevents the leakage current from developing a voltage on the first control electrode of the power transistor that exceeds the threshold voltage of the power transistor, wherein the protection circuit includes:
a first transistor having a third current electrode coupled to the first control electrode of the power transistor, a second control electrode, and a fourth current electrode coupled to the output of the first circuit, and
a current mirror circuit coupled to the first power supply terminal and having a first current mirror input coupled to the first control electrode of the power transistor, a second current mirror input coupled to receive a sleep signal, a first current mirror output coupled to the second control electrode of the first transistor, and a second current mirror output coupled to the output of the first circuit, wherein the current minor circuit comprises:
a current mirror coupled to the first power supply terminal having a first leg and a second leg;
a second transistor having a third control electrode as the first current mirror input, a fifth current electrode coupled to the first leg, and a sixth current electrode coupled to the second current minor output;
a load circuit having a first terminal coupled to the second control electrode of the first transistor and a second terminal coupled to the second current mirror output; and
an input transistor having a fourth control electrode as the second current mirror input, a seventh current electrode coupled to the second leg, and an eighth current electrode coupled to the first power supply terminal.
8. The first circuit of claim 7 , wherein the load circuit comprises a diode-connected transistor in series with a first resistance, wherein the diode-connected transistor and the first transistor have a same threshold voltage.
9. The first circuit of claim 8 , wherein the current minor circuit further comprises a third transistor coupled between the input transistor and the second leg, wherein the second leg is coupled to the seventh current electrode of the input transistor through the third transistor.
10. The first circuit of claim 9 , further comprising:
a second resistance having a first terminal coupled to the first power supply terminal and a second terminal;
a fourth transistor having a fifth control electrode for receiving a boosted voltage having a voltage level that is above a voltage level at the first power supply terminal, a ninth current electrode coupled to the second terminal of the second resistance; and a tenth current electrode; and
a fifth transistor coupled in series between the second current mirror output and the tenth current electrode of the fourth transistor.
11. A method that is for operating a power transistor using a sleep mode and an active mode, wherein during the sleep mode the power transistor has a leakage current between a control electrode and a current electrode, wherein the power transistor has a threshold voltage, comprising:
applying an input signal to the control electrode of the power transistor during the active mode;
detecting the leakage current during the sleep mode; and
responsive to detecting the leakage current, providing a current drain on the control electrode of the power transistor during the sleep mode of sufficient magnitude to pull down a voltage on the control electrode of the power transistor to ensure that the threshold voltage of the power transistor is not exceeded during the sleep mode.
12. The method of claim 11 , further comprising removing the current drain during the active mode.
13. The method of claim 12 , wherein the step of detecting comprises:
detecting the voltage on the control electrode of the power transistor; and
converting the voltage to a first current.
14. The method of claim 13 , wherein the step of providing a current drain comprises:
converting the first current to a second current; and
converting the second current to the current drain.
15. The method of claim 14 , wherein the step of converting the second current to the current drain comprises:
converting the second current to a bias voltage; and
converting the bias voltage to the current drain.
16. The method of claim 12 , further comprising using a current mirror circuit to detect the leakage current and to provide the current drain.
17. A power driver circuit having an active mode and a sleep mode for driving a power transistor having a first current electrode coupled to a first power supply terminal, a second current electrode for being coupled to a load, and a control electrode, wherein the power transistor is characterized by having a threshold voltage and a leakage current, wherein the leakage current occurs between the control electrode and the first current electrode during the sleep mode, comprising:
an amplifier having an output for being coupled to the control electrode of the power transistor, wherein the amplifier provides an active output during the active mode; and
a protection circuit means coupled to the output of the amplifier and to the control electrode of the power transistor, wherein the protection circuit is for detecting the leakage current and preventing the leakage current from developing a first voltage on the control electrode of the power transistor that exceeds the threshold voltage of the power transistor, wherein the protection circuit means prevents the leakage current from developing the first voltage by providing a current path to pull down a voltage on the control electrode of the power transistor.
18. The power driver circuit of claim 17 , wherein the protection circuit means prevents the leakage current from developing the voltage on the control electrode of the power transistor that exceeds the threshold voltage of the power transistor by establishing a current drain on the gate of the power transistor.
19. The power driver circuit of claim 17 , wherein the protection circuit means comprises:
a current drain circuit for being coupled to the control electrode of the power transistor; and
a current mirror circuit for being coupled to the control electrode of the power transistor and controlling the current drain circuit.
20. The power driver circuit of claim 19 wherein the current mirror circuit detects the leakage current and biases the current drain circuit based on the magnitude of the leakage current.