Computational generation of narrow-bandwidth digital signals
View Patent ↗A signal shaper generates an output signal representing a binary sequence, the output signal being the time-dependence of a signal value F. The signal shaper is input a first signal value F 0 and a different second signal value F 1 , and receives a sequence of data bits. If the state of a first data bit and the state of a second data bit differ, the signal shaper controls the signal value F to change monotonically from the first signal value F 0 or the second signal value F 1 at a first point in time via one or more intermediate values at intermediate points in time to the second signal value F 1 or the first signal value F 0 at a later second point in time. On the time interval from the first point in time to the second point in time, the output signal may be a monotonic step function.
1. A signal shaper for generating an output signal representing a binary sequence, the output signal being a time-dependence of a signal value F, comprising:
the signal shaper is configured to
receive a first signal value F 0 and a different second signal value F 1 ;
receive a sequence of data bits, each data bit having a state which is either “zero” or “one”, the sequence containing at least a first data bit and a subsequent second data bit;
determine the state of the first data bit and the state of the second data bit;
if the state of the first data bit and the state of the second data bit are determined to be “zero” and “one”, respectively, controlling the signal value F to change monotonically from the first signal value F 0 at a first point in time via one or more intermediate values at intermediate points in time to a second signal value F 1 at a later second point in time; and,
if the state of the first data bit and the state of the second data bit are determined to be “one” and “zero”, respectively, controlling the signal value F to change monotonically from the second signal value F 1 at the first point in time via one or more intermediate values at intermediate points in time to the first signal value F 0 at the second point in time, wherein the signal value F is an oscillation frequency delivered by a phase-locked loop; wherein the signal shaper is in an integrated circuit.
2. The signal shaper as claimed in claim 1 , wherein the signal value F is a frequency or amplitude of a voltage or current.
3. The signal shaper as claimed in claim 1 , wherein on a time interval from the first point in time to the second point in time the output signal is a monotonic step function.
4. The signal shaper as claimed in claim 1 , wherein the signal shaper comprises a clock for determining the intermediate points in time and the second point in time relative to the first point in time.
5. The signal shaper as claimed in claim 1 , wherein the signal shaper is configured to
receive the sequence of data bits in the form of a bit stream; and
recognize a bit rate of the bit stream;
and wherein the first point in time and the second point in time are separated by a time gap which is equal to the inverse of the bit rate.
6. The signal shaper as claimed in claim 1 , comprising a controller for controlling the oscillation frequency delivered by the phase-locked loop as a function of the received sequence of data bits.
7. The signal shaper as claimed in claim 6 , wherein the phase-locked loop comprises a frequency divider having a frequency ratio, the frequency ratio determining the oscillation frequency delivered by the phase-locked loop, and wherein the controller is capable of controlling the frequency ratio.
8. The signal shaper as claimed in claim 7 , wherein the controller is capable of generating a frequency ratio signal indicating an integer number to the frequency divider, the integer number defining the frequency ratio, wherein the controller is capable of varying the frequency ratio signal at a rate at least 50 times greater than the inverse of the time gap between the first point in time and the second point in time.
9. The signal shaper as claimed in claim 8 , wherein the controller comprises a sigma-delta modulator for generating the frequency ratio signal.
10. The signal shaper as claimed in claim 1 , wherein the signal shaper is the integrated circuit.
11. A communication system comprising a signal shaper as claimed in claim 1 .
12. The signal shaper as claimed in claim 1 , wherein the intermediate points in time comprise 2N+1 equidistant points in time at which the signal value F assumes the following values:
F 0 +ΔF/2 k+1 where k=0, . . . , N; and
F 1 −ΔF/2 k+1 where k=1, . . . , N;
N being an integer number equal to or greater than zero, and ΔF being the difference F 1 −F 0 .
13. A signal shaper for generating an output signal representing a binary sequence, the output signal being a time-dependence of a signal value F, comprising:
the signal shaper is configured to
receive a first signal value F 0 and a different second signal value F 1 ;
receive a sequence of data bits, each data bit having a state which is either “zero” or “one”, the sequence containing at least a first data bit and a subsequent second data bit;
determine the state of the first data bit and the state of the second data bit;
if the state of the first data bit and the state of the second data bit are determined to be “zero” and “one”, respectively, controlling the signal value F to change monotonically from the first signal value F 0 at a first point in time via one or more intermediate values at intermediate points in time to a second signal value F 1 at a later second point in time, wherein the intermediate points in time comprise 2N+1 equidistant points in time at which the signal value F assumes the following values:
F 0 +ΔF/2 k+1 where k=0, . . . , N; and
F 1 −ΔF/2 k+1 where k=1, . . . , N;
N being an integer number equal to or greater than zero, and ΔF being the difference F 1 −F 0 ; and,
if the state of the first data bit and the state of the second data bit are determined to be “one” and “zero”, respectively, controlling the signal value F to change monotonically from the second signal value F 1 at the first point in time via one or more intermediate values at intermediate points in time to the first signal value F 0 at the second point in time; wherein the signal shaper is in an integrated circuit.
14. A method of generating an output signal representing a binary sequence, the output signal being a time-dependence of a signal value F, the method comprising:
receiving a first signal value F 0 and a different second signal value F 1 ;
receiving a sequence of data bits, each data bit having a state which is either “zero” or “one”, the sequence containing at least a first data bit and a subsequent second data bit;
determining the state of the first data bit and the state of the second data bit;
if it is determined that the state of the first data bit and the state of the second data bit are “zero” and “one”, respectively, controlling the signal value F to change monotonically from the first signal value F 0 at a first point in time via one or more intermediate values at intermediate points in time to a second signal value F 1 at a later second point in time;
if it is determined that the state of the first data bit and the state of the second data bit are “one” and “zero”, respectively, controlling the signal value F to change monotonically from the second signal value F 1 at the first point in time via one or more intermediate values at intermediate points in time to the first signal value F 0 at the second point in time; and
controlling an oscillation frequency delivered by a phase-locked loop as a function of the received sequence of data bits.
15. An information carrier embodied in a non-transitory tangible medium carrying code portions for executing steps of a method as claimed in claim 14 when run on a programmable device.
16. The method of claim 14 , wherein the signal value F is the oscillation frequency delivered by the phase-locked loop.
17. The method of claim 16 , wherein the controlling the oscillation frequency delivered by the phase-locked loop comprises:
performing frequency division according to a frequency ratio, the frequency ratio determining the oscillation frequency delivered by the phase-locked loop.
18. The method of claim 17 , wherein the performing the frequency division comprises:
generating a frequency ratio signal indicating an integer number, the integer number defining the frequency ratio, and;
varying the frequency ratio signal at a rate at least 50 times greater than an inverse of a time gap between the first point in time and the second point in time.
19. The method of claim 18 , wherein the generating the frequency ratio signal comprises:
generating the frequency ratio signal using a sigma-delta modulator.
20. The method of claim 14 , further comprising:
receiving the sequence of data bits in the form of a bit stream; and
recognizing a bit rate of the bit stream, wherein the first point in time and the second point in time are separated by a time gap which is equal to an inverse of the bit rate.