Digital phase locked loop with reduced switching noise
View Patent ↗A method to operate a digital phase locked loop (DPLL) in which the DPLL includes a phase-frequency detector that compares the frequency of a reference signal with a feedback signal to generate an error signal. The error signal is used to generate first and second control words. Binary current control word bits and thermometric current control word bits are generated using the first and second control words, respectively. A binary controller switches a first set of binary current sources prior to a frequency lock being achieved using the binary current control word bits and the thermometric current control word bits are held at a predetermined value. After achieving the frequency lock, the binary current sources are fixed and then a thermometric controller switches a second set of thermometric current sources using the thermometric current control word bits. Operating the DPLL using the binary controller before the frequency lock and the thermometric controller after the frequency lock reduces switching noise and achieves stable loop dynamics.
1. A method for operating a digital phase locked loop (DPLL), the DPLL including a binary controller, a thermometric controller, a current controlled oscillator (CCO), and first and second sets of current sources, the method comprising:
generating an output signal by the CCO based on a magnitude of a current signal provided by the first and the second sets of current sources;
reducing a frequency of the output signal by a predetermined factor to generate a feedback signal;
comparing the frequency and phase of an externally generated reference signal with the feedback signal to generate an error signal;
generating first and second control words using the error signal, wherein the first and second control words have at least one bit;
generating binary current control word bits and thermometric current control word bits based on the first and second control words respectively;
controlling switching of the first set of current sources prior to a frequency lock using the binary current control word bits, wherein the thermometric current control word bits are fixed at a predetermined value, wherein the frequency lock represents a condition in which the frequency of the reference signal is equal to the frequency of the feedback signal; and
controlling switching of the second set of current sources subsequent to the frequency lock based on the thermometric current control word bits, wherein the binary current control word bits are fixed when the frequency lock is achieved.
2. The method for operating a DPLL of claim 1 , further comprising converting the error signal to a digital signal prior to generating the first and second control words.
3. The method for operating a DPLL of claim 1 , wherein the second control word is thermometrically coded prior to the switching of the second set of current sources by the thermometric controller.
4. The method for operating a DPLL of claim 1 , wherein current sources of the first set of current sources are binary weighted.
5. The method for operating a DPLL of claim 1 , wherein the magnitude of the current signals generated by the current sources of the second set of current sources are identical.
6. The method for operating a DPLL of claim 1 , wherein the binary controller and the thermometric controller are digital to analog current sources.
7. The method for operating a DPLL of claim 1 , further comprising detecting the frequency lock with a frequency lock detector.
8. The method for operating a DPLL of claim 1 , wherein the output signal generated by the CCO is an oscillating signal.
9. A digital phase locked loop (DPLL) that receives a reference signal generated by an external source and generates an output signal, the DPLL comprising:
a current controlled oscillator (CCO), connected to first and second sets of current sources, that generates the output signal based on a magnitude of currents generated by the first and second sets of current sources;
a loop divider, connected to the CCO, that receives the output signal and reduces a frequency thereof by a predetermined factor to generate a feedback signal;
a phase-frequency detector (PFD), connected to the loop divider, that receives and compares the reference signal and the feedback signal and generates an error signal;
a time-to-digital converter (TDC), connected to the PFD, that converts the error signal to a digital error signal;
a digital filter, connected to the TDC, that generates first and second control words based on the digital error signal, wherein the first and second control words have at least one bit;
a binary to thermometric converter, connected to the digital filter, that thermometrically codes the second control word;
a binary controller, connected to the digital filter and the first set of current sources, for generating binary current control word bits based on the first control word, wherein the binary current control word bits are used to control switching of the first set of current sources before a frequency lock has been achieved, wherein the frequency lock represents a condition in which the frequency of the reference signal is equal to the frequency of the feedback signal; and
a thermometric controller, connected to the second set of current sources and the binary to thermometric converter, for generating thermometric current control word bits based on the second control word, wherein the thermometric current control word bits are used to control switching of the second set of current sources after attainment of the frequency lock.
10. The DPLL of claim 9 , wherein the PFD operates at the positive edge of the reference signal.
11. The DPLL of claim 9 , wherein the digital filter operates at the negative edge of the reference signal.
12. The DPLL of claim 9 , wherein the output signal generated by the CCO is an oscillating signal.
13. The DPLL of claim 9 , further comprising a frequency lock detector, connected to the PFD and the binary and thermometric controllers, for detecting the frequency lock and indicating said frequency lock to the binary and thermometric controllers.
14. The DPLL of claim 9 , wherein current sources of the first set of current sources are binary weighted.
15. The DPLL of claim 9 , wherein current sources of the second set of current sources are thermometrically weighted.
16. The DPLL of claim 9 , wherein the binary and thermometric controllers are digital to analog current sources.
17. The DPLL of claim 16 , wherein currents generated by the binary and thermometric controllers have substantially the same unit step so that the frequency lock and a phase lock loop have substantially the same loop dynamics.
18. A digital phase lock loop (DPLL) that receives a reference signal generated by an external source and generates an oscillating output signal, the DPLL comprising:
a current controlled oscillator (CCO), connected to first and second sets of current sources that generate currents received by the CCO, wherein the CCO generates the oscillating output signal based on a magnitude of the currents generated by the first and second sets of current sources;
a loop divider, connected to the CCO, that receives the output signal and reduces a frequency thereof by a predetermined factor to generate a feedback signal;
a phase-frequency detector (PFD), connected to the loop divider, that receives and compares the reference signal and the feedback signal and generates an error signal;
a time-to-digital converter (TDC), connected to the PFD, that converts the error signal to a digital error signal;
a digital filter, connected to the TDC, that generates first and second control words based on the digital error signal, wherein the first and second control words have at least one bit;
a binary to thermometric converter, connected to the digital filter, that thermometrically codes the second control word;
a frequency lock detector, connected to the PFD, for detecting a frequency lock in which the frequency of the reference signal is equal to the frequency of the feedback signal;
a binary controller, connected to the digital filter and the first set of current sources, for generating binary current control word bits based on the first control word, wherein the binary current control word bits are used to control switching of the first set of current sources before achieving a frequency lock, wherein the frequency lock represents a condition in which the frequency of the reference signal is equal to the frequency of the feedback signal; and
a thermometric controller, connected to the second set of current sources and the binary to thermometric converter, for generating thermometric current control word bits based on the second control word, wherein the thermometric current control word bits are used to control switching of the second set of current sources after achieving the frequency lock.
19. The DPLL of claim 18 , wherein current sources of the first set of current sources are binary weighted.
20. The DPLL of claim 19 , wherein current sources of the second set of current sources are thermometrically weighted.