Soft program of a non-volatile memory block
View Patent ↗A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.
1. A method, comprising:
erasing bits in a memory block;
identifying bits that have been over-erased;
soft programming a first subset of the bits that have been over-erased;
measuring results of soft programming the first subset of bits;
selecting an initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits; and
soft programming a second subset of bits that have been over-erased while applying the initial voltage condition to the bits in the second subset of bits, wherein the second subset comprises bits that are still over-erased when the step of selecting occurs.
2. The method of claim 1 , further comprising:
determining if there is a third subset of bits within the second subset of bits that need further soft programming; and
if there is a third subset of bits, soft programming the third subset of bits using a voltage condition applied to the bits of the third subset of bits that includes a higher voltage than the initial voltage condition.
3. The method of claim 1 , wherein the bits have gates and the soft programming the first subset of bits comprises using an initial conservative gate voltage applied to the gates of over-erased bits of a first page, wherein the over-erased bits of the first page are within the first subset of bits.
4. The method of claim 3 , wherein if the step of measuring determines that the over-erased bits of the first page are not sufficiently soft programmed, the soft programming the first subset of bits further comprises using a first increased voltage applied to the gates of over-erased bits of a second page, wherein the over-erased bits of the second page are within the first subset of bits.
5. The method of claim 4 , wherein if the step of measuring determines that the over-erased bits of second page are not sufficiently soft programmed, the soft programming the first subset of bits further comprises using a second increased voltage greater than the first increased voltage applied to the gates of over-erased bits of a third page, wherein the over-erased bits of the third page are within the first subset of bits.
6. The method of claim 5 , wherein the step of selecting comprises selecting, as the initial voltage condition, the gate voltage used during a soft programming step that results in at least a predetermined percentage of the bits being increased above a minimum desired threshold voltage for being erased to at least a first threshold voltage that is less than a maximum desired threshold voltage for being erased.
7. The method of claim 1 , wherein the step of identifying bits that have been over-erased is further characterized as identifying bits that have been over-erased by less than a predetermined amount.
8. The method of claim 7 , wherein the step of soft programming a first subset of the bits is further characterized by the first subset of bits being characterized as comprising only bits that have been over-erased by less than the predetermined amount.
9. The method of claim 1 , further comprising determining if the soft programming the second subset results in all of the bits having a threshold voltage between a first threshold voltage and a second threshold voltage greater than the first threshold voltage, wherein an over-erased condition is present in a bit if the bit has a threshold voltage below the first threshold voltage.
10. The method of claim 9 , further comprising continuing soft programming using increasing voltage conditions until all of the bits have a threshold voltage between the first threshold voltage and the second threshold voltage.
11. A method, comprising:
erasing a block of memory cells in which a first plurality of the memory cells are erased to have a threshold voltage between a first threshold and a second threshold voltage less than the first threshold voltage, a second plurality of memory cells are erased to have a threshold voltage between the second threshold voltage and a third threshold voltage less than the second threshold voltage, and a third plurality of memory cells to have a threshold voltage less than the third threshold voltage;
determining a response of a portion of the second plurality of memory cells to soft programming;
selecting a soft programming condition based on the response of the portion of the second plurality of memory cells to the soft programming; and
applying the programming condition that was selected in the step of selecting to the memory cells in the second subset that still have a threshold voltage between the second and third threshold voltage and to the third plurality.
12. The method of claim 11 , wherein the programming condition that was selected was an initial gate voltage.
13. The method of claim 11 , further comprising performing soft programming until all of the memory cells are between the first threshold voltage and the second threshold voltage.
14. The method of claim 11 , wherein determining a response comprises performing soft programming until a sample of the second plurality responds with a result of at least a predetermined fraction of the memory cells in the sample having a threshold voltage between a fourth threshold voltage and the first threshold voltage, wherein the fourth threshold voltage is less than the first threshold voltage and greater than the second threshold voltage.
15. The method of claim 14 , wherein the selecting the soft programming condition comprises selecting a gate voltage, which was applied to gates of memory cells in the sample, used during the soft programming that resulted in at least half of the memory cells in the sample having a threshold voltage between a fourth threshold voltage and the first threshold voltage.
16. The method of claim 15 wherein the fourth threshold voltage is halfway between the first and second threshold voltages.
17. The method of claim 16 wherein the predetermined fraction is one half.
18. A method, comprising:
erasing all bits in a memory block;
identifying which bits in the memory block that have been over-erased by the erasing;
testing a portion of the bits in the memory block that have been over-erased by the erasing to determine a desired gate voltage applied during soft programming that will result in increasing a threshold voltage of at least a predetermined percentage of the bits tested with soft programming at the desired gate voltage to at least an intermediate threshold voltage between a lowest desirable threshold voltage and a maximum desirable threshold voltage; and
using the desired gate voltage applied to gates of the bits for soft programming all of the remaining over-erased bits.
19. The method of claim 18 , wherein the testing comprises applying increasing gate voltages for soft programming samples of bits until the desired gate voltage is reached for a sample of bits.
20. The method of claim 19 , wherein the soft programming is applied to samples of over-erased bits that have at least a minimum threshold voltage.