Granted Patent B2

US 8,532,583 · App. 13/003,951 · Granted Sep 10, 2013

Abstract

Claims (44)

1. A semiconductor device comprising first synthesized frequency generation logic arranged to receive a reference signal, and to generate a first synthesized frequency signal from the reference signal;

wherein the first synthesized frequency generation logic comprises first programmable divider logic arranged to receive the reference signal and to generate a first divided signal comprising a frequency with a period equal to N times that of the reference signal, where N comprises a first programmable integer value; and

the first synthesized frequency generation logic is further arranged to generate the first synthesized frequency signal comprising a frequency with a period equal to 1/M that of the first divided signal, where M comprises a further programmable integer value.

2. The semiconductor device of claim 1 wherein the semiconductor device further comprises programmable oscillator control logic, operably coupled to an oscillator arranged to generate the reference signal, the programmable oscillator control logic being arranged to programmably control a frequency of the reference signal generated by the oscillator.

3. The semiconductor device of claim 2 wherein the programmable oscillator control logic comprises a Phased-Locked Loop (PLL), programmable by way of a tuning control.

4. The semiconductor device of claim 3 wherein the programmable oscillator control logic comprises a fractional ‘N’ divider and the programmable oscillator control logic is programmable by controlling a divide ratio used by the fractional ‘N’ divider.

5. The semiconductor device of claim 2 wherein the programmable oscillator control logic is programmable by way of an Absolute Radio Frequency Channel Number (ARFCN) input signal.

6. The semiconductor device of claim 2 wherein the programmable oscillator control logic is arranged to programmably control a frequency of the reference signal generated by the oscillator over approximately a 4% range thereof.

7. The semiconductor device of claim 1 wherein the first synthesizer frequency generation logic comprises a Delay-Locked Loop (DLL).

8. The semiconductor device of claim 1 wherein the first synthesizer frequency generation logic comprises:

delay elements, the delay elements arranged to receive the first divided signal generated by the programmable divider logic; and

logic to generate at least M component signals comprising corresponding edge transitions separated in time by T/M, where T is a period of the divided signal (f div ).

9. The semiconductor device of claim 8 wherein the first synthesizer frequency generation logic further comprises digital processing logic arranged to receive the at least M component signals, and logic to generate the synthesized frequency signal based at least partly on a combination of the component signals provided thereto by selecting those component signals to output.

10. The semiconductor device of claim 1 wherein the semiconductor device comprises radio frequency, RF, transceiver circuitry arranged to support RF communication within a Universal Mobile Telecommunications System, UMTS.

11. The semiconductor device of any claim 1 wherein the synthesized frequency generation logic module generates a first synthesized frequency signal from the reference signal, and a second synthesized frequency logic is arranged to receive the reference signal and to generate a second synthesized frequency signal from the reference signal; and the programmable divider logic generates a first divided signal comprising a frequency with a period equal to N rx times that of the reference signal, and the synthesized frequency signal comprises a frequency with a period equal to 1/M rx that of the divided signal; and

the second synthesized frequency logic comprises second programmable divider logic arranged to receive the reference signal and to generate a second divided signal comprising a frequency with a period equal to N tx times that of the reference signal, such that the second synthesized frequency generation logic is further arranged to generate the second synthesized frequency signal comprising a frequency with a period equal to 1/M tx that of the second divided signal;

where N rx , N tx , M rx and M tx each comprise a programmable integer value.

12. The semiconductor device of claim 11 wherein the first synthesized frequency signal is used for down converting a received Radio Frequency, RF, signal to a receive chain intermediate frequency signal, and the second synthesized frequency signal is used for up converting a transmit chain intermediate frequency signal to an RF signal to be transmitted.

13. The semiconductor device of claim 12 wherein the semiconductor device further comprises frequency error correction logic arranged to introduce a frequency error correction offset into at least one from a group of:

the receive chain intermediate frequency signal; and

the transmit chain intermediate frequency signal.

14. The semiconductor device of claim 13 wherein frequency error correction is performed within a digital domain.

15. A method for generating a synthesized frequency signal, the method comprising:

configuring an oscillator to generate a reference signal;

generating a first divided signal comprising a frequency with a period equal to N times that of the reference signal; and

generating a first synthesized frequency signal comprising a frequency having a period equal to 1/M that of the first divided signal, where M comprises a further programmable integer value.

16. The method of claim 15 wherein:

the first divided signal comprises a frequency having a period equal to N rx times that of the reference signal and the first synthesized frequency signal comprises a frequency with a period equal to 1/M rx that of the first divided signal; wherein

the method further comprises:

generating a second divided signal comprising a frequency with a period equal to N tx times that of the reference signal, and

generating a second synthesized frequency signal comprising a frequency with a period equal to 1/M tx that of the second divided signal;

where N rx , N tx , M rx and M tx each comprise a programmable integer value.

17. A semiconductor device comprising:

a phase locked loop (PLL) arranged to programmably control a VCO to provide a reference signal;

a first frequency generator comprising a first programmable divider arranged to receive the reference signal and to generate a first divided signal with a period equal to N rx times that of the reference signal, wherein the first frequency generator is arranged to generate a first frequency signal with a period equal to 1/M rx that of the first divided signal; and

a second frequency generator comprising a second programmable divider arranged to receive the reference signal and to generate a second divided signal with a period equal to N tx times that of the reference signal, wherein the second frequency generator is arranged to generate a second frequency signal with a period equal to 1/M tx that of the second divided signal;

wherein N rx , M rx , N tx , and M tx , each comprise a programmable integer value.

18. The semiconductor device of claim 17 , wherein the PLL is further arranged to control a frequency of the reference signal generated by the VCO.

19. The wireless communication device of claim 17 , wherein the first frequency generator further comprises:

delay elements arranged to receive the first divided signal; and

logic to generate at least M rx component signals comprising corresponding edge transitions separated in time by T/M rx , where T is a period of the divided signal.

20. The semiconductor device of claim 19 , wherein the first frequency generator further comprises:

digital processing logic arranged to receive the at least M rx component signals; and

a signal combiner arranged to generate the first frequency signal based on a combination of the component signals by selecting the combination of component signals to output.

Assignments (30)