Granted Patent B2

US 9,236,372 · App. 13/193,855 · Granted Jan 12, 2016

Abstract

Claims (34)

1. An integrated circuit electrostatic discharge (ESD) protection device comprising:

a power supply conductor;

a conductive pad;

an output buffer transistor formed in a first layout area and electrically coupled between the power supply conductor and the conductive pad, the output buffer transistor comprising a MOSFET gate electrode coupled to receive a control signal and formed over a substrate with a conductive gate finger which separates a source region and a drain region of a first conductivity type formed in the substrate; and

a gated diode formed in the same first layout area as the output buffer transistor and electrically connected as an ESD diode between the power supply conductor and the conductive pad, the gated diode comprising the drain region that is electrically connected to the conductive pad and a corresponding body tie region of a second conductivity type that is formed in the substrate and that is electrically connected to the power supply conductor such that the body tie region is separated from the drain region of the output buffer transistor by a diode finger formed over the substrate that is not electrically connected to the conductive gate finger of the output buffer transistor, where a mask element formed on the drain region separates a first silicide region adjacent the conductive gate finger from a second silicide region adjacent the diode finger, where the diode finger is one of a plurality of U-shaped conductive diode fingers, each formed with a single continuous first conductor layer and interleaved with and parallel to the conductive gate finger formed with a single continuous second conductor layer that is separate from the first conductor layer.

2. The integrated circuit ESD protection device of claim 1 , where the output buffer transistor comprises an NMOS transistor coupled between a VSS power supply conductor and the conductive pad.

3. The integrated circuit ESD protection device of claim 1 , where the drain region of the output buffer transistor comprises a drain-side resistive element.

4. The integrated circuit ESD protection device of claim 1 , wherein the gated diode is implemented as a plurality of parallel connected diodes defined by the plurality of diode fingers, wherein each of the plurality of parallel connected diodes comprises a gated diode inherent to the output buffer transistor for conducting ESD current.

5. The integrated circuit ESD protection device of claim 1 , wherein the gated diode is formed by a P-N junction between a P-well and an N+ diffusion region that functions as the drain of the output buffer transistor.

6. The integrated circuit ESD protection device of claim 1 , where the MOSFET gate electrode comprises a multi-fingered MOSFET gate electrode formed with a plurality of conductive gate fingers.

7. The integrated circuit ESD protection device of claim 1 , where the substrate is electrically coupled to the power supply conductor.

8. An integrated circuit device comprising:

a first pad conductor;

a power supply conductor;

a MOSFET transistor formed in a substrate region of a first conductivity type, the transistor comprising a gate electrode and source and drain regions of a second conductivity type formed in the substrate region, where the drain region is electrically coupled to the first pad conductor, the substrate region is electrically coupled to the power supply conductor, and the gate electrode is formed over the substrate region with a conductive gate finger which separates the source and drain regions; and

a gated diode structure formed in the same substrate region as the MOSFET transistor and electrically connected as an ESD diode between the first pad conductor and power supply conductor, the gated diode structure comprising:

a body tie region of the first conductivity type formed in the substrate region that is electrically connected to the power supply conductor,

the MOSFET transistor drain region of the second conductivity type that is electrically connected to the first pad conductor, and

a diode finger formed over the substrate region in parallel with the conductive gate finger to separate the body tie region and MOSFET transistor drain region, where a mask element formed on the MOSFET transistor drain region separates a first silicide region adjacent the conductive gate finger from a second silicide region adjacent the diode finger, where the diode finger is one of a plurality of U-shaped conductive diode fingers, each formed with a single continuous first conductor layer and interleaved with and parallel to the conductive gate finger formed with a single continuous second conductor layer that is separate from the first conductor layer.

9. The integrated circuit device of claim 8 , where the first pad conductor comprises an input/output pad conductor.

10. The integrated circuit device of claim 8 , where the power supply conductor is electrically connected to a power supply.

11. The integrated circuit device of claim 8 , where the MOSFET transistor comprises an NMOS transistor coupled between a VSS power supply conductor and the first pad conductor.

12. The integrated circuit device of claim 8 , where the drain region of the MOSFET transistor comprises a drain-side resistive element.

13. The integrated circuit device of claim 8 , where the conductive gate finger is one of a plurality of conductive gate fingers electrically coupled together and located in parallel.

14. The integrated circuit device of claim 8 , where the diode finger comprises a dielectric layer, a polysilicon layer, one or more metal layers, or a resistor-protect-oxide (RPO) layer.

15. The integrated circuit device of claim 8 , further comprising a metal-based contact layer formed on the MOSFET transistor drain region that is shared between the MOSFET transistor and gated diode structure and that is connected to the first pad conductor.

16. A method for forming a semiconductor device comprising:

forming a first well region of a first conductivity type in a first semiconductor substrate;

forming a patterned gate electrode finger layer and a separate floating patterned diode finger layer over at least part of the first well region, where the separate floating patterned diode finger is one of a plurality of U-shaped conductive diode finger layers, each formed with a single continuous first conductor layer and interleaved with and parallel to the patterned gate electrode finger layer formed with a single continuous second conductor layer that is separate from the first conductor layer;

forming source and drain regions of a second opposite conductivity type in the first well region and adjacent to the patterned gate electrode finger layer, thereby defining an output buffer MOSFET transistor;

forming a mask element over a shared drain region between the patterned gate electrode finger layer and the separate floating patterned diode finger layer;

forming a body tie region of the first conductivity type in the first well region and adjacent to the patterned diode finger layer, thereby defining a gated diode between the body tie region and the shared drain region such that the gated diode is coupled in parallel with the output buffer MOSFET transistor; and

forming one or more conductive layers to connect the body tie region to a power supply conductor and to connect the shared drain region to a conductive pad so that the gated diode is electrically connected as an ESD diode between the power supply conductor and the conductive pad.

17. The method of claim 16 , where forming one or more conductive layers comprises forming a silicide layer to partially cover the shared drain region except where covered by the mask element, thereby defining a drain-side resistive element.

Assignments (21)