Guard ring integrated LDMOS
View Patent ↗An LDMOSFET transistor ( 100 ) is provided which includes a substrate ( 101 ), an epitaxial drift region ( 104 ) in which a drain region ( 116 ) is formed, a first well region ( 107 ) in which a source region ( 112 ) is formed, a gate electrode ( 120 ) formed adjacent to the source region ( 112 ) to define a first channel region ( 14 ), and a grounded substrate injection suppression guard structure that includes a patterned buried layer ( 102 ) in ohmic contact with an isolation well region ( 103 ) formed in a predetermined upper region of the substrate so as to be spaced apart from the first well region ( 107 ) and from the drain region ( 116 ), where the buried layer ( 102 ) is disposed below the first well region ( 107 ) but not below the drain region ( 116 ).
1. A semiconductor device, comprising:
a substrate of a first conductivity type;
a first semiconductor region of a second conductivity type different from the first conductivity type located in the substrate;
a first well region of the first conductivity type located in the substrate adjacent to the first semiconductor region;
a first source region of the second conductivity type located in a predetermined upper region of the first well region;
a drain region of the second conductivity type located in a predetermined upper region of the first semiconductor region, the drain region being spaced a predetermined distance from the first well region;
a gate electrode located over a gate insulating layer and having an edge substantially aligned with an edge of the source region, thereby defining a first channel region inside the first well region; and
a substrate injection suppression feature of the second conductivity type located in the substrate, wherein the substrate injection suppression feature comprises a buried layer and a conductive vertical portion conductively coupled to the buried layer, wherein the buried layer is disposed below the first well region but not below the drain region.
2. The device of claim 1 , where the first conductivity type impurities comprise p-type impurities, and the second conductivity type impurities comprise n-type impurities.
3. The device of claim 1 , wherein the first semiconductor region comprises an n-type drift region located at the substrate surface to surround the drain region.
4. The device of claim 1 , wherein the first semiconductor region comprises an n-type epitaxial layer.
5. The device of claim 1 , where the first well region comprises a p-type high voltage region located at the substrate surface to surround the source region.
6. The device of claim 1 , further comprising a conductive isolation region located at the substrate surface and surrounded by the conductive vertical portion.
7. The device of claim 6 , where the conductive isolation region is electrically shorted to the source region.
8. The device of claim 1 , where the buried layer from the substrate injection suppression feature has a terminal end that is substantially aligned with an edge of the first well region that is located between the source and drain regions.
9. The device of claim 1 , where the buried layer from the substrate injection suppression feature has a dopant charge density on the order of 5E14 to 5E16 cm −2 .
10. The device of claim 1 , wherein the conductive vertical portion extends from a surface of the region down to the buried layer.
11. The device of claim 1 , where the substrate injection suppression feature suppresses substrate injection from the drain region and controls an amount of parasitic current injected into the substrate from a parasitic vertical NPN transistor formed with the drain region.
12. A method for forming a semiconductor device, comprising in any order:
forming in a semiconductor substrate a first body region of a first conductivity type that is disposed to surround a designated source region area;
forming in the first body region a first source region of a second conductivity type different from the first conductivity type;
forming in the semiconductor substrate a semiconductor drift layer of the second conductivity type that is disposed adjacent to the first body region to surround a designated drain region area;
forming in the semiconductor drift layer a drain region of the second conductivity type, the drain region being spaced a predetermined distance from the first body region;
forming in the semiconductor substrate a buried substrate injection suppression layer of the second conductivity type, where the buried layer is disposed under at least the first body region but not under the designated drain region area;
forming in the semiconductor substrate a conductive well region of the second conductivity type that is conductively coupled to the buried substrate injection suppression layer; and
forming a gate electrode over at least part of the first body region and semiconductor drift layer that is disposed substantially adjacent to the source region, thereby defining a first channel region inside the first body region.
13. The method of claim 12 , where forming the buried substrate injection suppression layer comprises:
forming a first patterned implant mask over the semiconductor substrate that is patterned to have an opening to overlap with at least the first body region but not with the designated drain region area; and
implanting impurities into the semiconductor substrate to form the buried substrate injection suppression layer using the first patterned implant mask as a mask for ion implantation.
14. The method of claim 13 , where forming the conductive well region layer comprises:
forming a second patterned implant mask over the semiconductor substrate that is patterned to have an opening to overlap with a portion of the buried substrate injection suppression layer; and
implanting impurities into the semiconductor substrate to form the conductive well region layer using the second patterned implant mask as a mask for ion implantation.
15. The method of claim 12 , where forming the buried substrate injection suppression layer comprises selectively implanting one or more buried layers having a first overall lateral extent that is substantially parallel to the substrate surface and that substantially aligns with an edge of the first body region that is located between the source and drain regions.
16. The method of claim 12 , further comprising forming one or more conductive layers over the semiconductor substrate to electrically connect the source region to an isolation terminal of the second conductivity type formed in the conductive well region layer.
17. A semiconductor device, comprising:
one or more source regions of a first conductivity type located in a substrate of a second conductivity type different from the first conductivity type;
one or more gate electrodes located over the substrate, each gate electrode being disposed adjacent to a corresponding source region;
one or more drain regions of the first conductivity type, each drain region being disposed adjacent to a corresponding gate electrode; and
a conductive isolation feature of the first conductivity type, wherein the conductive isolation feature includes one or more buried layers and a sinker well conductively coupled to the one or more buried layers, wherein each of the one or more buried layers is disposed below the one or more source regions but not below the one or more drain regions.
18. The device of claim 17 , further comprising:
one or more body regions of the second conductivity type disposed in the substrate to surround the one or more source regions; and
one or more drift regions of the first conductivity type disposed in the substrate to surround the one or more drain regions.
19. The device of claim 18 , where the conductive isolation feature comprises one or more buried finger layers extending under the one or more source regions but not under the one or more drain regions to form a single conductive substrate injection suppression feature that suppresses substrate injection from the one or more drain regions and suppresses a vertical parasitic bipolar transistor.
20. The device of claim 19 , further comprising a conductive isolation region formed in the sinker well, wherein the conductive isolation region is electrically coupled to one or more source regions.