Granted Patent B2

US 8,504,886 · App. 13/191,456 · Granted Aug 6, 2013

Abstract

Claims (20)

1. A method of scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device, the method comprising:

identifying one or more scan partitions in the embedded logic circuit, wherein each of the identified scan partitions comprises at least one scan chain, wherein each of the at least one scan chain comprises a plurality of scan registers;

identifying one or more interacting registers connecting the scan registers of a scan chain of a first scan partition and a scan chain of a second scan partition;

defining an interacting scan chain comprising a combination of the identified interacting registers; and

testing at least one of the embedded logic circuit, the plurality of scan registers and the identified interacting registers by selectively activating the scan chains of the first and the second scan partitions and the interacting scan chain,

wherein testing the embedded logic circuit comprises testing the embedded logic circuit in the first scan partition by activating the at least one scan chain of the first scan partition and the interacting scan chain.

2. The method of claim 1 , wherein each of the plurality of scan registers comprises a flip-flop.

3. A method of scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device, the method comprising:

identifying one or more scan partitions in the embedded logic circuit, wherein each of the identified scan partitions comprises at least one scan chain, wherein each of the at least one scan chain comprises a plurality of scan registers;

identifying one or more interacting registers connecting the scan registers of a scan chain of a first scan partition and a scan chain of a second scan partition;

defining an interacting scan chain comprising a combination of the identified interacting registers; and

testing at least one of the embedded logic circuit, the plurality of scan registers and the identified interacting registers by selectively activating the scan chains of the first and second scan partitions and the interacting scan chain, and

wherein testing the plurality of scan registers further comprises testing the scan registers of the at least one scan chain of the first scan partition, and

wherein testing the plurality of scan registers of the at least one scan chain of the first scan partition comprises activating the at least one scan chain of the first scan partition and the interacting scan chain.

4. A method of scan partitioning for testing an embedded logic circuit in an integrated circuit (IC) device, the method comprising:

identifying one or more scan partitions in the embedded logic circuit, wherein each of the identified scan partitions comprises at least one scan chain, wherein each of the at least one scan chain comprises a plurality of scan registers;

identifying one or more interacting registers connecting the scan registers of a scan chain of a first scan partition and a scan chain of a second scan partition;

defining an interacting scan chain comprising a combination of the identified interacting registers; and

testing at least one of the embedded logic circuit, the plurality of scan registers and the identified interacting registers by selectively activating the scan chains of the first and the second scan partitions and the interacting scan chain, wherein testing the plurality of scan registers comprises testing the scan registers of the interacting scan chain.

5. The method of claim 4 , wherein testing the plurality of scan registers of the interacting scan chain comprises activating the interacting scan chain and the at least one scan chain of the second scan partition.

Assignments (31)