Adaptive write procedures for non-volatile memory
View Patent ↗A method includes performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump. A portion of the write operation is performed on the memory cells of the memory array using the voltage of the charge pump. A level of the voltage is compared to a reference. If the level of the voltage is below the reference, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells, wherein the reduced number of memory cells is a first subset of the memory cells.
1. A method of performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump, the method comprising:
performing a portion of the write operation on the memory cells of the memory array using the voltage of the charge pump;
comparing a level of the voltage to a reference; and
if the level of the voltage is below the reference, continuing the write operation with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells, wherein the reduced number of memory cells is a first subset of the memory cells.
2. The method of claim 1 , wherein the performing the write operation comprises performing a program procedure.
3. The method of claim 2 , wherein the memory cells are arranged in a plurality of pages, wherein each page has a plurality of the memory cells, wherein the performing a portion comprises performing the program operation on a first page.
4. The method of claim 1 , wherein the performing the portion of the write operation comprises performing an erase procedure.
5. The method of claim 1 , wherein the performing the portion of the write operation is further characterized by the write operation comprising one of a group consisting of a soft programming procedure and a pre-programming procedure.
6. The method of claim 1 , wherein the write operation further comprises:
completing the write operation on the first subset of the memory cells using the voltage, and
performing the write operation on a second subset of the memory cells using the voltage.
7. The method of claim 1 , wherein the performing the portion of the write operation comprises performing a portion of a write procedure, wherein the write procedure comprises applying a first number of pulses of the voltage and the portion of the write procedure comprises applying a second number of pulses of the voltage, wherein the second number is less than the first number.
8. The method of claim 7 , wherein the comparing is performed in response to the second number of pulses occurring during the performing a portion.
9. The method of claim 1 , wherein the performing a portion of the write operation comprises beginning an erase procedure, further comprising:
after the continuing the write operation, determining if the voltage being used on the first subset of memory cells is below the reference voltage; and
if the voltage being used on the first subset of memory cells is below the reference voltage, continuing the write operation using the voltage of the charge pump on a second subset of the memory cells, wherein the second subset is a subset of the first subset.
10. The method of claim 9 , further comprising:
completing erasing the second subset of memory cells; and
completing erasing the memory cells by sequentially erasing groups of memory cells, wherein each group has a same number of memory cells as the second subset.
11. The method of claim 10 , wherein the write operation further comprises:
pre-programming the memory cells prior to beginning the erase procedure; and
soft programming selected memory cells after the completing the erasing of the memory cells.
12. A method of performing a write operation on memory cells of a memory array to a first logic state using a voltage of a charge pump, the method comprising:
performing a portion of the write operation on the memory cells of the memory array using the voltage of the charge pump;
in response to completing the performing the portion, comparing the voltage to a reference voltage; and
if the voltage has a magnitude less than a magnitude of the reference voltage, continuing the write operation on a decreased number of the memory cells, wherein the decreased number of the memory cells comprise a subset of the memory cells.
13. The method of claim 12 , wherein the performing a portion comprises applying a predetermined number of pulses of the voltage of the charge pump.
14. The method of claim 13 , wherein the write operation comprises a program operation.
15. The method of claim 13 , wherein the write operation comprises an erase operation.
16. The method of claim 15 , wherein continuing the write operation comprises completing an erase procedure.
17. The method of claim 15 , wherein continuing the writing operation comprises:
performing a portion of an erase procedure;
in response to completing the performing the portion of the erase procedure, comparing the voltage to the reference; and
if the voltage has a magnitude less than the magnitude of the reference voltage, continuing the erase procedure on a decreased number of the memory cells relative to the first subset, wherein the decreased number of the memory cells relative to the first subset comprise a subset of the first subset of memory cells.
18. The method of claim 17 , further comprising:
completing the erase procedure on the second subset;
dividing the memory cells, less the second subset of memory cells, into groups of equal size and equal to the second subset; and
sequentially performing the erase procedure on the groups.
19. A non-volatile memory system, comprising:
an array of memory cells that are non-volatile;
charge pumps that have outputs that provide a voltages for a write operation; and
a controller that causes the output to be coupled to the memory cells to perform a write to a first logic state on the memory cells, determines if loading by the memory cells results is excessive by comparing the voltage to a reference, and if the loading is excessive, the write operation is continued with an increased level of the voltage by reducing load on the charge pump by providing the voltage on a reduced number of memory cells, wherein the reduced number of memory cells is a first subset of the memory cells.
20. The non-volatile memory system of claim 19 , wherein the controller determines if the loading is excessive in response to a predetermined number of pulses of the voltage occurring.