Multi-gate semiconductor devices
View Patent ↗A semiconductor device includes a substrate, a source region formed over the substrate, a drain region formed over the substrate, a first gate electrode over the substrate adjacent to the source region and between the source and drain regions, and a second gate electrode over the substrate adjacent to the drain region and between the source and drain regions.
1. A semiconductor device comprising:
a substrate having a first dopant type;
a first gate electrode formed over the substrate;
a second gate electrode formed over the substrate and spatially separated from the first gate electrode, wherein the first gate electrode has a first length and the second gate electrode has a second length, the second length being substantially different from the first length;
a first region of a second dopant type formed in the substrate between and partially underlying the first and second gate electrodes, the first region having a first dopant concentration;
a separation region of the second dopant type formed in the first region, the separation region being spaced apart from the first and second gate electrodes and having a second dopant concentration that is greater than the first dopant concentration;
a source region formed in the semiconductor substrate on an opposing side of the first gate electrode from the first region, the source region having the second dopant type; and
a drain region formed in the semiconductor substrate on an opposing side of the second gate electrode from the first region, the drain region having the second dopant type.
2. The semiconductor device of claim 1 , wherein the device comprises a dual gate MOS transistor, wherein the first gate electrode serves as a channel region and the second gate electrode serves as an extended drain.
3. The semiconductor device of claim 2 , wherein the separation region is a highly doped region that electrically connects the channel region and the extended drain.
4. The semiconductor device of claim 2 , wherein the extended drain is lightly doped.
5. The semiconductor device of claim 1 , wherein the first length is at least 50 percent greater than the second length.
6. A semiconductor device comprising:
a substrate having a first dopant type;
a source region formed in the substrate;
a drain region formed in the substrate;
a first gate electrode of a first length over the substrate adjacent to the source region and between the source and drain regions;
a second gate electrode of a second length that is substantially different from the first length over the substrate adjacent to the drain region and between the source and drain regions, wherein the second gate electrode is spatially separated from the first gate electrode;
a first region of a second dopant type formed in the substrate between the first and second gate electrodes, the first region having a first dopant concentration; and
a separation region of the second dopant type formed in the first region, the separation region having a second dopant concentration that is greater than the first dopant concentration.
7. The semiconductor device of claim 6 , wherein the first length is greater than the second length.
8. The semiconductor device of claim 7 , wherein the first length is at least 50 percent greater than the second length.
9. The semiconductor device of claim 6 , wherein the first and second lengths are less than 0.2 microns.
10. The semiconductor device of claim 6 , wherein the first dopant type is P-type and the second dopant type is N-type.
11. The semiconductor device of claim 6 , further comprising a gate dielectric formed between each of the first and second gate electrodes and the substrate.
12. A semiconductor device comprising:
a semiconductor substrate having a first dopant type;
a source region having a second dopant type formed in the semiconductor substrate;
a drain region having the second dopant type formed in the semiconductor substrate;
a first region of a second dopant type and a first dopant concentration formed in the substrate between the source and drain regions;
a separation region having the second dopant type and a second dopant concentration that is greater than the first dopant concentration formed in the first region;
a first gate electrode formed over the semiconductor substrate adjacent to the source region, partially overlying the first region and spaced apart from the separation region; and
a second gate electrode formed over the semiconductor substrate adjacent to the drain region, partially overlying the first region and spaced apart from the separation region.
13. The semiconductor device of claim 12 , wherein the first gate electrode has a first length and the second gate electrode has a second length, the first length being at least 50 percent greater than the second length.
14. The semiconductor device of claim 13 , wherein the second length is less than 0.2 microns.
15. The semiconductor device of claim 12 , wherein the first dopant type is P-type and the second dopant type is N-type.
16. The semiconductor device of claim 12 , wherein the first gate electrode has a first length and the second gate electrode has a second length, the first length being approximately the same as the second length.