IP Library Granted Patent US 8,329,509
Granted Patent B2
US 8,329,509 · App. 12/752,717 · Granted Dec 11, 2012

Packaging process to create wettable lead flank during board assembly

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Quick Facts
Patent No.
US 8,329,509
App. No.
12/752,717
Granted
Dec 11, 2012
Kind
B2
Abstract

A method and apparatus are described for fabricating a low-pin-count chip package ( 701 ) including a die pad ( 706 ) for receiving an integrated circuit device and a plurality of connection leads ( 702 ) having recessed lead ends ( 704 ) at the outer peripheral region of each contact lead. After forming the package body ( 202 ) over the integrated circuit device, unplated portions ( 104 ) of the exposed bottom surface of the selectively plated lead frame are partially etched to form recessed lead ends ( 302 ) at the outer peripheral region of each contact lead, and the recessed lead ends are subsequently re-plated ( 402 ) to provide wettable recessed lead ends at the outer peripheral region of each contact lead.

Claims (39)

1. A method for making a recessed wettable lead end during package assembly, comprising:

providing a selectively plated lead frame strip having opposing first and second sides, the selectively plated lead frame strip comprising a die pad for receiving an integrated circuit die and a plurality of contact leads extending toward the die pad from an attached frame, where each contact lead has a first plating coating formed on the second side in a first region but not on an second peripheral region;

forming a package body over the first side of the selectively plated lead frame strip to encapsulate an integrated circuit die attached to the die pad while leaving exposed the plurality of contact leads on the second side of the selectively plated lead frame strip;

partially etching the second peripheral regions on the second surface of the plurality of contact leads that are not protected by the first plating coating to form a recessed lead end at the second peripheral region of each contact lead; and

forming a second plating coating on at least the recessed lead end of each contact lead to form a wettable recessed lead end at the second peripheral region of each contact lead.

2. The method of claim 1 , where providing the selectively plated lead frame strip comprises providing a copper lead frame strip formed to define a plated die pad, a plurality of partially plated separate copper contact leads, and an unplated copper frame.

3. The method of claim 1 , where forming the package body comprises overmolding or transfer molding a composite material to cover each integrated circuit die attached to the die pad while leaving exposed the plurality of separate contact leads on the second surface of the selectively plated lead frame strip.

4. The method of claim 1 , where partially etching the frame and the second peripheral regions comprises half-etching copper from the frame and the second peripheral regions on the second surface of the plurality of separate contact leads that are not protected by the first plating coating.

5. The method of claim 1 , where forming a second plating coating comprises applying a metal coating comprising tin or nickel to cover the recessed lead end of each contact lead and a partially etched portion of the frame.

6. The method of claim 1 , further comprising, after forming the second plating coating, cutting through the package body and the lead frame strip to leave each contact lead with a portion of the wettable recessed lead end at the second peripheral region of each contact lead.

7. The method of claim 6 , where cutting through the package body and the lead frame strip comprises performing a saw cut or laser cut or other singulation process.

8. The method of claim 1 , where partially etching the frame and the second peripheral forms the recessed lead end at the second peripheral region of each contact lead having an etch depth of approximately 50 microns.

9. A method of making a quad flat no-lead chip package comprising:

providing an array of lead frames integrally connected together and having opposing first and second sides, each lead frame comprising an outer frame, a die pad disposed within the outer frame, and a plurality of leads attached to the outer frame and extending toward the die pad, where a plating layer is selectively formed on the first side of the lead frame strip to leave an exposed lead frame strip region on the outer frame and at least a first portion of each lead immediately adjacent to the outer frame;

connecting a plurality of integrated circuit die to the array of lead frames so that, in each lead frame, an integrated circuit die is affixed to the die flag;

encapsulating the plurality of integrated circuit die with a molding compound formed on the second side of the array of lead frames while leaving exposed the exposed lead frame strip region on the first side of the array of lead frames;

partially etching the exposed lead frame strip region to form a recessed lead frame strip region on the first side of the array of lead frames;

plating the recessed lead frame strip region with a wettable material to form a plated recessed lead frame strip region; and

cutting through the molding compound and the array of lead frames in the plated recessed lead frame strip region to leave each lead with a portion of the plated recessed lead frame strip region at an outer peripheral region.

10. The method of claim 9 , where connecting the plurality of integrated circuit die to the array of lead frames comprises:

attaching an integrated circuit die to each die pad of the array of lead frames; and

electrically coupling each integrated circuit die to a corresponding plurality of leads associated with the attached integrated circuit die.

11. The method of claim 9 , where providing the array of lead frames comprises providing an array of copper lead frames with each copper lead frame comprising an unplated copper outer frame, a plated copper die pad disposed within the unplated copper outer frame, and a plurality of partially plated copper leads attached to the unplated copper outer frame, where each of the partially plated copper leads has a first unplated portion immediately adjacent to the unplated copper outer frame such that the exposed lead frame strip region is defined by the unplated copper outer frame and the first unplated portion of each partially plated copper lead.

12. The method of claim 9 , where partially etching the exposed lead frame strip region comprises applying a persulfate salt etch chemistry that is selective to the plating layer to form the recessed lead frame strip region on the first side of the array of lead frames.

13. The method of claim 9 , where partially etching the exposed lead frame strip region comprises half-etching copper from the exposed lead frame strip region on the first side of the array of lead frames.

14. The method of claim 9 , where plating the recessed lead frame strip region comprises applying a metal coating comprising tin or nickel to plate the recessed lead frame strip region.

15. The method of claim 9 , where cutting through the molding compound and the array of lead frames comprises performing a saw cut or laser cut or other singulation process.

16. A method for packaging a semiconductor chip comprising:

providing a lead frame strip having a package body formed on a first side of the lead frame strip, where the lead frame strip comprises a plurality of outer frame members, each of which comprises a plurality of leads connected to the outer frame member and extending inwardly therefrom on a second side of the lead frame strip, with a metal coating formed on a first portion of each lead but not on an second peripheral portion of each lead;

partially etching areas on the second side of the lead frame strip without protection of the metal coating such that a recess is formed in at least the second peripheral portion of each lead;

forming a first metal coating in the recess to form a plated recess in at least the second peripheral portion of each lead; and

cutting along each outer frame member to separate the plurality of leads such that each separated lead includes a portion of the plated recess at a peripheral end exposed by said cutting.

17. The method of claim 16 , where providing a lead frame strip comprises:

providing a lead frame strip comprising a plurality of outer frame members, each of which comprises a plurality of leads connected to the outer frame member and extending inwardly on a second side of the lead frame strip,

forming a metal coating on a first portion of each lead but not on an second peripheral portion of each lead; and

forming a package body on the first side of the lead frame strip.

18. The method of claim 16 , where partially etching areas on the second side of the lead frame strip comprises half etching each outer frame member and second peripheral portion of each lead not covered with the metal coating on the second side of the lead frame strip.

19. The method of claim 16 , where forming the first metal coating comprises plating the recess with a metal coating comprising tin or nickel.

20. The method of claim 16 , where cutting along the outer frame member comprises performing a saw cut or laser cut or other singulation process.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2010
From: GONG, ZHIWEI; BONDA, NAGESWARA RAO; GAO, WEI; WANG, JINSHENG; YE, DEHONG
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 024176/0414 →