Area-efficient high voltage bipolar-based ESD protection targeting narrow design windows
View Patent ↗An area-efficient, high voltage, single polarity ESD protection device ( 300 ) is provided which includes an p-type substrate ( 303 ); a first p-well ( 308 - 1 ) formed in the substrate and sized to contain n+ and p+ contact regions ( 310, 312 ) that are connected to a cathode terminal; a second, separate p-well ( 308 - 2 ) formed in the substrate and sized to contain only a p+ contact region ( 311 ) that is connected to an anode terminal; and an electrically floating n-type isolation structure ( 304, 306, 307 - 2 ) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.
1. An integrated circuit device, comprising:
first and second terminals;
a single polarity electrostatic discharge (ESD) clamp coupled between the first and second terminals, comprising:
(a) a substrate;
(b) a first semiconductor region of a first conductivity type formed in the substrate;
(c) a second semiconductor region of the first conductivity type formed in the substrate and separated from the first semiconductor region; and
(d) a third semiconductor region of a second conductivity type opposite from the first conductivity type formed in the substrate to surround and separate the first and second semiconductor regions;
where the first semiconductor region comprises a first contact region of the first conductivity type connected to the first terminal and a second contact region of the second conductivity type connected to the first terminal, and
where the second semiconductor region comprises a third contact region of the first conductivity type connected to the second terminal and no additional contact region of the second conductivity type connected to the second terminal.
2. The integrated circuit device of claim 1 , where the first conductivity type is p-type, and the second conductivity type is n-type.
3. The integrated circuit device of claim 1 , wherein the first and second semiconductor regions each comprise a heavily doped p-well formed at a surface of the substrate.
4. The integrated circuit device of claim 1 , wherein the first and second semiconductor regions each comprise a heavily doped p-well formed in a p-type epitaxial layer having relatively lighter doping.
5. The integrated circuit device of claim 1 , wherein the third semiconductor region comprises a heavily doped n-type well formed at the surface of the substrate to separate the first and second semiconductor regions.
6. The integrated circuit device of claim 5 , wherein the third semiconductor region comprises a heavily doped n-type buried layer formed below the first and second semiconductor regions and in ohmic contact with the heavily doped n-type well.
7. The integrated circuit device of claim 5 , wherein the third semiconductor region comprises an n-well region formed at the surface of the substrate in ohmic contact with the heavily doped n-type well and separated from the first semiconductor region by a spacing dimension which controls an avalanche breakdown region between the first semiconductor region and the n-well region.
8. The integrated circuit device of claim 1 , wherein the first terminal is electrically coupled to a ground reference potential and the second terminal is electrically coupled to a node in a circuit that is to be protected against a voltage exceeding a trigger voltage value such that current associated with the voltage automatically flows through the single polarity ESD clamp when the voltage exceeding the trigger voltage value is placed across the first and second terminals.
9. The integrated circuit device of claim 1 , wherein the first semiconductor region is sized at a first relatively larger area to accommodate both the first and second contact regions, while the second semiconductor region is sized at a second relatively smaller area to accommodate only the third contact region.
10. The integrated circuit device of claim 1 , where there are no additional contact regions for any terminal in the single polarity ESD clamp.
11. The integrated circuit device of claim 1 , further comprising a fourth semiconductor region of the second conductivity type formed at the surface of the substrate in ohmic contact with the third semiconductor region and separated from the first semiconductor region by a spacing dimension which controls an avalanche breakdown region between the first semiconductor region and the fourth semiconductor region.
12. A method of fabricating a semiconductor device, comprising:
forming first and second regions of a first conductivity type at a surface of a substrate so that the first and second regions are spaced apart from one another by at least a portion of a semiconductor region of a second, opposite conductivity type and so that the first region has a larger area than the second region at a surface of the semiconductor region;
forming a first contact region of the first conductivity type in each of the first and second regions, respectively;
forming a second contact region of the second conductivity type in only the first region but not in the second region; and
forming first and second terminals such that the first terminal is in electrical contact with the first and second contact regions formed in the first region and the second terminal is in electrical contact with the first contact region formed in the second region, thereby forming a single polarity electrostatic discharge (ESD) clamp coupled between the first and second terminals.
13. The method of fabricating a semiconductor device according to claim 12 , where the first conductivity type is p-type, and the second conductivity type is n-type.
14. The method of fabricating a semiconductor device according to claim 12 , where forming first and second regions comprises forming first and second p-wells at the surface of the substrate.
15. The method of fabricating a semiconductor device according to claim 12 , where forming first and second regions comprises forming a heavily doped p-well in a p-type epitaxial layer having relatively lighter doping.
16. The method of fabricating a semiconductor device according to claim 12 , where forming first and second regions comprises forming an electrically floating semiconductor region of the second conductivity type in the substrate to surround and separate the first and second regions.
17. The method of fabricating a semiconductor device according to claim 16 , where forming the electrically floating semiconductor region comprises forming a heavily doped n-type well at the surface of the substrate to separate the first and second regions.
18. The method of fabricating a semiconductor device according to claim 17 , wherein forming the electrically floating semiconductor region comprises forming a heavily doped n-type buried layer below the first and second regions and in ohmic contact with the heavily doped n-type well.
19. The method of fabricating a semiconductor device according to claim 17 , wherein forming the electrically floating semiconductor region comprises forming an n-well region at the surface of the substrate in ohmic contact with the heavily doped n-type well and separated from the first region by a spacing dimension which controls an avalanche breakdown region between the first region and the n-well region.
20. The method of fabricating a semiconductor device according to claim 12 , where there are no additional contact regions for any terminal in the single polarity ESD clamp.
21. The method of fabricating a semiconductor device according to claim 12 , where forming first and second terminals comprises forming the second terminal in electrical contact with only the first contact region formed in the second region.