IP Library Granted Patent US 8,572,345
Granted Patent B2
US 8,572,345 · App. 13/234,305 · Granted Oct 29, 2013

Memory management unit (MMU) having region descriptor globalization controls and method of operation

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Quick Facts
Patent No.
US 8,572,345
App. No.
13/234,305
Granted
Oct 29, 2013
Kind
B2
Abstract

Embodiments of computer processing systems and methods are provided that include a memory protection unit (MPU), and a plurality of region descriptors associated with the MPU. The region descriptors include address range and translation identifier values for a respective region of memory. Control logic determines whether a translation identifier control indicator is in a first state, and if the translation identifier control indicator is in the first state, the control logic allows a first process being executed by the processing system to access a memory region allocated to a second process being executed by the processing system.

Claims (53)

1. A computer processing system comprising:

a memory protection unit (MPU);

a plurality of region descriptors associated with the MPU, wherein the region descriptors include address range and translation identifier values for a respective region of memory;

a translation identifier control indicator (TIDCTL); and

control logic operable to determine whether the translation identifier control indicator is in a first state, and if the translation identifier control indicator is in the first state, allow a first process being executed by the processing system to access a memory region allocated to a second process of the processing system.

2. The system of claim 1 wherein:

the control logic masks a portion of one or more of the plurality of region descriptors corresponding to the second process if the translation identifier control indicator is in the first state.

3. The system of claim 2 wherein:

the portion of the region descriptor that is masked is a translation identifier value (TID).

4. The system of claim 1 further comprising:

a region globalization control enable indicator (RGCEN);

a process identifier (PID); and

control logic operable to determine whether the region globalization control enable indicator is in a first state, and if the region globalization control enable indicator is not in the first state, allow the first process to access the memory region allocated to the second process according to whether the TIDCTL indicator is in the first state.

5. The system of claim 4 further comprising:

the region descriptors include a region globalization control indicator (RGC) that indicates whether a respective region descriptor can be utilized by other processes when the globalization indicator is in a first state.

6. The system of claim 1 further comprising:

a globalization process identifier (G_PID) field in a control register; and

control logic operable to use globalization masking for translation identifier (TID) comparisons when the translation identifier control indicator is in the first state, and a process identifier (PID) value of the first process matches a value in the G_PID field.

7. The system of claim 1 further comprising:

control logic operable to use globalization masking for translation identifier (TID) comparisons when the translation identifier control indicator is in the first state and the first process is in supervisor mode.

8. The system of claim 1 further comprising:

a memory protection unit enable (MPUEN) indicator in a control register, wherein when the MPUEN indicator is in a first state, access addresses of the first process are compared to addresses in one or more of the plurality of region descriptors to determine whether there is a match.

9. The system of claim 8 further wherein:

when no match is detected, and an access type is not enabled to bypass MPU protections, then an exception condition is signaled for an access attempt.

10. A computer processing system comprising:

a memory protection unit (MPU);

a control register including a globalization process identifier (G_PID) field;

a plurality of region descriptors associated with the MPU, wherein at least one of the region descriptors is allocated to a first process; and

control logic operable to allow the first process to access a region of memory allocated for a second process when a process identifier (PID) for the first process matches a value in the G_PID field.

11. The system of claim 10 further comprising:

a translation identifier control indicator (TIDCTL); and

control logic operable to mask translation identifier values (TIDs) in one or more of the plurality of region descriptors for the first and second processes when the translation identifier control (TIDCTL) indicator is in a first state and the first process is in supervisor mode.

12. The system of claim 10 wherein:

the control logic masks a portion of a region descriptor used for the second process if a translation identifier control indicator (TIDCTL) is in a first state.

13. The system of claim 12 wherein:

the portion of the region descriptor that is masked is a translation identifier value (TID).

14. The system of claim 12 further comprising:

one or more of the plurality of region descriptors include a region globalization control indicator (RGC) that indicates whether a memory region defined in the respective region descriptor can be utilized by other processes.

15. The system of claim 14 further comprising:

the control register includes a region globalization control enable indicator (RGCEN); and

control logic operable to determine whether the region globalization control enable indicator is in a first state, and if the region globalization control enable indicator is not in the first state, allow the first process to access the memory region allocated to the second process according to whether the TIDCTL indicator is in the first state.

16. The system of claim 14 further comprising:

initializing a memory protection unit enable (MPUEN) indicator in the control register, wherein when the MPUEN indicator is in a first state, comparing access addresses to an address range specified in one or more of the plurality of region descriptors to determine whether there is a match; and

when no match is detected, and an access type is not enabled to bypass MPU protections, then an exception condition is signaled for an access attempt.

17. A method comprising:

initializing a translation identifier control (TIDCTL) indicator in a control register of a memory protection unit (MPU) in a computer system; and

when the TIDCTL indicator is in a first state, masking translation identifier comparisons in one or more of a plurality of region descriptors of the MPU for first and second processes to allow the first process to access a memory region allocated to the second process.

18. The method of claim 17 further comprising:

initializing a region globalization control enable (RGCEN) indicator in the control register; and

when the RGCEN and TIDCTL indicators are both in a specified state, the masking the translation identifiers is performed based on whether a region globalization control (RGC) indicator in the region descriptor for the second process is in a specified state.

19. The method of claim 17 further comprising:

initializing a globalization process identifier (G_PID) in the control register to specify a process identifier (PID) for the second process; and

initializing a memory protection unit enable (MPUEN) indicator in the control register, wherein when the MPUEN indicator is in a first state, comparing access addresses to address ranges defined by one or more of the plurality of region descriptors to determine whether there is a match.

Assignments (23)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2025
From: NXP USA, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
Reel/Frame 072889/0893 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 16, 2011
From: MOYER, WILLIAM C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 026918/0011 →