Lead frame for semiconductor package
View Patent ↗A lead frame for providing electrical interconnection to an Integrated Circuit (IC) die. The lead frame includes a die support area for receiving and supporting the IC die and a plurality of leads surrounding the die support area. A plurality of interconnect receiving portions is formed in the die support area. The interconnect receiving portions are for providing electrical interconnection to first bumps on a bottom surface of the IC die. The leads are for providing electrical interconnection to second bumps on a surface of the IC die, the second bumps surrounding the first bumps.
1. A lead frame for providing electrical interconnection to an Integrated Circuit (IC) die, the lead frame comprising:
a die support area for receiving and supporting the IC die;
a plurality of interconnect receiving portions formed in the die support area, the interconnect receiving portions for providing electrical interconnection to first bumps on a bottom surface of the IC die; and
a plurality of leads surrounding the die support area, the leads for providing electrical interconnection to second bumps on a surface of the IC die, wherein the second bumps surround the first bumps,
wherein an outer lead portion of the leads is formed in a first plane and an inner lead portion of the leads is formed in a second plane that is down-set from the first plane such that a die alignment feature is defined in the leads.
2. The lead frame of claim 1 , wherein a plurality of dimples is formed adjacent respective ones of the interconnect receiving portions.
3. The lead frame of claim 2 , wherein the dimples are formed by stamping.
4. The lead frame of claim 2 , wherein the dimples allow the interconnect receiving portions to be electrically isolated from each other when a bottom surface of the interconnect receiving portions is removed, wherein the removed portions extend in a vertical direction from a bottom surface of the die receiving area to a bottom surface of the dimples.
5. The lead frame of claim 1 , wherein the interconnect receiving portions are formed in a matrix arrangement in the die support area.
6. The lead frame of claim 1 , wherein the interconnect receiving portions are formed in a central portion of the die support area.
7. A lead frame, comprising:
a die support area;
a plurality of interconnect receiving portions formed in the die support area, wherein the interconnect receiving portions are arranged to receive a plurality of flip chip bumps of a flip chip die; and
a plurality of leads surrounding the die support area, wherein an outer lead portion of the leads is formed in a first plane and an inner lead portion of the leads is formed in a second plane that is down-set from the first plane such that a die alignment feature is defined in the leads.
8. The lead frame of claim 7 , wherein a plurality of dimples is formed adjacent respective ones of the interconnect receiving portions.
9. The lead frame of claim 8 , wherein the dimples are formed by stamping or etching.
10. The lead frame of claim 7 , wherein the interconnect receiving portions are formed in a matrix arrangement in the die support area.
11. The lead frame of claim 7 , wherein the interconnect receiving portions are formed in a central portion of the die support area.
12. A semiconductor package, comprising:
a lead frame having a die support area, a plurality of interconnect receiving portions formed in the die support area, and a plurality of leads surrounding the die support area, wherein an outer lead portion of the leads is formed in a first plane and an inner lead portion of the leads is formed in a second plane that is down-set from the first plane such that a die alignment feature is defined in the leads;
an integrated circuit (IC) die attached to the die support area of the lead frame and electrically connected to the interconnect receiving portions; and
a molding compound encapsulating the IC die and a portion of the lead frame.
13. The semiconductor package of claim 12 , further comprising a plurality of input/output (IO) terminals formed on a surface of the semiconductor package and a plurality of external leads extending from a plurality of sides of the semiconductor package.
14. The semiconductor package of claim 12 , wherein a plurality of dimples is formed adjacent respective ones of the interconnect receiving portions.
15. The semiconductor package of claim 12 , wherein the interconnect receiving portions are formed in a matrix arrangement in the die support area of the lead frame.
16. The semiconductor package of claim 12 , wherein the IC die is a flip chip die.
17. The semiconductor package of claim 16 , wherein the interconnect receiving portions are arranged to receive a plurality of flip chip bumps on the flip chip die.
18. The semiconductor package of claim 12 , wherein the interconnect receiving portions are formed in a central portion of the die support area of the lead frame.