Error detection in a content addressable memory (CAM) and method of operation
View Patent ↗A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM) includes providing comparand data to the CAM, comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry. In response to asserting the match signal, the method further includes providing output data, an output parity bit, and an output complement parity bit from the RAM, using the comparand data to generate a generated parity bit, and providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit. The error indicator may indicate an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.
1. A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM), the method comprising:
providing comparand data to the CAM;
comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry;
in response to asserting the match signal, providing output data, an output parity bit, and an output complement parity bit from the RAM;
using the comparand data to generate a generated parity bit; and
providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit.
2. The method of claim 1 , wherein the error indicator indicates an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.
3. The method of claim 1 , further comprising:
in response to asserting the match signal, providing mask data from the RAM, wherein the using the comparand data to generate a generated parity bit comprises using the comparand data and the mask data to generate the generated parity bit.
4. The method of claim 1 , further comprising:
storing write data and corresponding parity data and complement parity data to the CAM system.
5. The method of claim 4 , wherein a first portion of the write data is stored in the CAM, a second portion of the write data is stored in the RAM, and the corresponding parity data and complement parity data are stored in the RAM.
6. The method of claim 5 , wherein the corresponding parity data and the complement parity data are stored in a same bitcell of the RAM.
7. The method of claim 4 , wherein the write data includes mask data.
8. The method of claim 1 , wherein each of the output data, the output parity bit and the output complement parity bit is provided as a result of a wired-OR operation.
9. The method of claim 1 , wherein when the step of comparing the comparand data to entries of the CAM to determine the matching CAM entry results in asserting the match signal corresponding to the matching CAM entry and asserting a second match signal corresponding to an incorrect matching CAM entry, the error signal indicates an error based on the generated parity bit, the output parity bit, and the output complement parity bit.
10. The method of claim 9 , wherein a first parity bit stored in a first RAM entry corresponding to the matching CAM entry is a logic level one and a second parity bit stored in a second RAM entry corresponding to the incorrect matching CAM entry is a logic level zero.
11. The method of claim 10 , wherein the output parity bit is provided from the RAM as a logical ORing of at least the first parity bit and the second parity bit.
12. A method for accessing a content addressable memory (CAM) system having a CAM and random access memory (RAM), the method comprising:
storing write data and corresponding parity data and complement parity data to the CAM system, wherein a first portion of the write data is stored in the CAM, a second portion of the write data is stored in the RAM, and the corresponding parity data and complement parity data are stored in the RAM;
providing comparand data to the CAM;
comparing the comparand data to entries of the CAM to determine a matching CAM entry and asserting a match signal corresponding to the matching CAM entry;
in response to asserting the match signal, providing output data, an output parity bit, and an output complement parity bit from the RAM;
using the comparand data to generate a generated parity bit; and
providing an error indicator based on the generated parity bit, the output parity bit, and the output complement parity bit wherein the error indicator indicates an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.
13. The method of claim 12 , further comprising:
in response to asserting the match signal, providing mask data from the RAM, wherein the using the comparand data to generate a generated parity bit comprises using the comparand data and the mask data to generate the generated parity bit.
14. The method of claim 12 , wherein the corresponding parity data and the complement parity data are stored in a same bitcell of the RAM.
15. The method of claim 12 , wherein when the step of comparing the comparand data to entries of the CAM to determine the matching CAM entry results in asserting the match signal corresponding to the matching CAM entry and asserting a second match signal corresponding to an incorrect matching CAM entry, the error signal indicates the error.
16. The method of claim 15 , wherein a first parity bit stored in a first RAM entry corresponding to the matching CAM entry is a logic level one and a second parity bit stored in a second RAM entry corresponding to the incorrect matching CAM entry is a logic level zero.
17. The method of claim 12 , wherein each of the output data, the output parity bit and the output complement parity bit is provided as a result of a wired-OR operation.
18. A content addressable memory (CAM) system, comprising:
a CAM having a plurality of CAM entries and providing a plurality of match signals, wherein in response to receiving comparand data, the CAM compares the comparand data to the plurality of CAM entries to determine a matching CAM entry and asserts a match signal of the plurality of match signals corresponding to the matching CAM entry;
a random access memory (RAM) coupled to the CAM and having a plurality of RAM entries, wherein each RAM entry corresponds to a corresponding CAM entry of the plurality of CAM entries and wherein each RAM entry stores data, a parity bit, and a complement parity bit, wherein, in response to the asserted match signal of the plurality of match signals from the CAM, the RAM provides output data, an output parity bit, and an output complement parity bit;
a parity generator, wherein the parity generator uses the comparand data to generate a generated parity bit; and
error detection logic coupled to the parity generator and the RAM, wherein the error detection logic indicates an error when the generated parity bit is not equal to the output parity bit or when the output parity bit is equal to the output complement parity bit.
19. The CAM system of claim 18 , wherein, for each RAM entry of the RAM, the parity bit and the complement parity bit are stored in a same bitcell of the RAM.
20. The CAM system of claim 18 , wherein each RAM entry also stores one or more mask bits, and wherein, in response to the asserted match signal, the RAM provides one or more output mask bits, and wherein the parity generator uses the one or more output mask bits and the comparand data to generate the generated parity bit.