Method for reducing plasma discharge damage during processing
View Patent ↗A semiconductor process and apparatus to provide a way to reduce plasma-induced damage by applying a patterned layer of photoresist which includes resist openings formed over the active circuit areas as well as additional resist openings formed over inactive areas in order to maintain the threshold coverage level to control the amount of resist coverage over a semiconductor structure so that the total amount of resist coverage is at or below a threshold coverage level. Where additional resist openings are required in order to maintain the threshold coverage level, these openings may be used to create additional charge dissipation structures for use in manufacturing the final structure.
1. A method for designing a patterned photoresist layer for at least a first circuit block of a wafer, the method comprising:
computing a coverage value for a mask layout used to pattern a photoresist layer on at least a first circuit block of a wafer based on an area computation for all openings defined in the mask layout; and
generating a modified mask layout to include one or more additional openings located over one or more inactive circuit areas and re-computing the coverage value for the modified mask layout based on an area computation for all openings defined in the mask layout until the coverage value is at or below a first predetermined coverage threshold value.
2. The method of claim 1 , further comprising iteratively repeating the computing and generating steps after reducing the first predetermined coverage threshold value until a modified mask layout is generated that meets a predetermined design limit.
3. The method of claim 2 , where the predetermined design limit comprises a layout constraint, an implant uniformity requirement, or a resist penetration requirement.
4. The method of claim 2 , further comprising designing the patterned photoresist layer for a second circuit block of a wafer, comprising:
computing a second coverage value for the mask layout used to pattern the photoresist layer on the second circuit block of the wafer; and
generating a modified mask layout to include one or more additional openings located over one or more inactive circuit areas in the second circuit block and re-computing the second coverage value for the modified mask layout based on an area computation for all openings defined in the mask layout until the second coverage value is at or below a second predetermined coverage threshold value which is different from the first predetermined coverage threshold value.
5. The method of claim 4 , where the first predetermined coverage threshold value is used to generate the modified mask layout for a digital circuit block, and where the second predetermined coverage threshold value is used to generate the modified mask layout for an analog circuit block, such that the second predetermined coverage threshold value is less than the first predetermined coverage threshold value.
6. The method of claim 1 , further comprising manufacturing an integrated circuit using the modified mask layout which includes the one or more additional openings located over one or more inactive circuit areas.