Digital method to obtain the I-V curves of NVM bitcells
View Patent ↗A calibration table ( 160 ) of reference current (Iref) values and associated digital register settings is used during user test/diagnostics mode by varying the Iref values by changing the digital register settings and searching the transitioning gate voltage (Vg) of each bitcell at each Iref value to obtain the bitcell I-V curve using a digitally tunable gate voltage control ( 117 ) and reference current circuit ( 123 ) under control of a test module or circuit ( 110 ).
1. A method for generating current-voltage characteristic information for a non-volatile memory bitcell, comprising:
generating a selected reference current corresponding to a selected digital register setting;
comparing the selected reference current to a drain current generated by a non-volatile memory bitcell as a sweeping gate voltage is applied to the non-volatile memory bitcell until a transitioning gate voltage is identified; and
storing the transitioning gate voltage and selected reference current as current-voltage characteristic information for the non-volatile memory bitcell.
2. The method of claim 1 , further comprising obtaining a calibration table from test flash memory comprising a plurality of reference current values and a corresponding plurality of digital register settings.
3. The method of claim 2 , where obtaining the calibration table comprises:
setting a digital register setting for a digitally trim-able reference current circuit to a first value;
measuring a reference current generated by the digitally trim-able reference current circuit; and
saving the measured reference current and first value as a value pair in the calibration table.
4. The method of claim 1 , where generating the selected reference current comprises applying the selected digital register setting to a digitally trim-able reference current circuit to generate the selected reference current.
5. The method of claim 1 , where comparing the selected reference current to a drain current of the non-volatile memory bitcell comprises applying the selected reference current and the drain current of the non-volatile memory bitcell to a sense amplifier circuit.
6. The method of claim 1 , where comparing the selected reference current to a drain current of the non-volatile memory bitcell comprises performing one address reads of the non-volatile memory bitcell at a plurality of gate voltages.
7. The method of claim 1 , where the sweeping gate voltage is applied to the non-volatile memory bitcell by increasing the gate voltage from low to high until the drain current generated by the non-volatile memory bitcell is larger than the selected reference current so that a sense amplifier output of the bitcell changes from logic 0 to 1.
8. The method of claim 1 , where the sweeping gate voltage is applied to the non-volatile memory bitcell by decreasing the gate voltage from high to low until the drain current generated by the non-volatile memory bitcell is smaller than the selected reference current so that a sense amplifier output of the bitcell changes from logic 1 to 0.
9. The method of claim 1 , further comprising:
generating a second reference current corresponding to a different digital register setting;
comparing the second reference current to a drain current generated by a non-volatile memory bitcell as a sweeping gate voltage is applied to the non-volatile memory bitcell until a second transitioning gate voltage is identified; and
storing the second transitioning gate voltage and second reference current as current-voltage characteristic information for the non-volatile memory bitcell, thereby defining a plurality of current-voltage curve points for the non-volatile memory bitcell.
10. The method of claim 1 , where storing the transitioning gate voltage and selected reference current comprises storing the transitioning gate voltage and selected reference current as a point on a current-voltage curve for the non-volatile memory bitcell.
11. A memory device, comprising:
a plurality of non-volatile memory bitcells arranged in an array of rows and columns;
a calibration table memory storing a plurality of digital register settings corresponding to a plurality of reference current values;
a reference current generator circuit for generating a selected reference current corresponding to a selected digital register setting from the calibration table memory;
a gate voltage generator circuit for generating a plurality of sweeping gate voltages;
a row decoder for applying the plurality of sweeping gate voltages to the selected non-volatile memory bitcell; and
a sense amplifier circuit for comparing the selected reference current to a drain current generated by the selected non-volatile memory bitcell as the plurality of sweeping gate voltages are applied to the selected non-volatile memory bitcell until a transitioning gate voltage is identified.
12. The memory device of claim 11 , further comprising a memory for storing a plurality of current-voltage value pairs comprising a first selected reference current value and a corresponding first transitioning gate voltage.
13. The memory device of claim 11 , further comprising one or more data output ports for outputting a plurality of current-voltage value pairs comprising a first selected reference current value and a corresponding first transitioning gate voltage.
14. The memory device of claim 11 , where the plurality of non-volatile memory bitcells comprises a plurality of non-volatile semiconductor memory transistors arranged in rows and columns, each said memory transistor comprising a source, a drain, and a gate, said gate being a floating gate injectable with electrons and being dischargeable, wherein gates of all transistors in each row of semiconductor memory transistors are connected to a corresponding word line, wherein drains of all transistors in each column are connected to a corresponding bit line, and wherein sources of all transistors in each row are connected to a corresponding source control line.
15. The memory device of claim 11 , where the calibration table memory comprises a non-volatile test flash memory.
16. The memory device of claim 11 , where the reference current generator circuit comprises a digitally tunable reference current circuit.
17. The memory device of claim 11 , where the sense amplifier circuit outputs a first logic state when the drain current generated by the selected non-volatile memory bitcell is less than the selected reference current, and outputs a second logic state when the drain current generated by the selected non-volatile memory bitcell is higher than the reference current.
18. A method for obtaining current-voltage curve data points for one or more non-volatile memory bitcells, comprising:
generating a predetermined reference current;
applying predetermined source and drain voltages to a selected non-volatile memory bitcell;
applying a sweeping gate voltage to the selected non-volatile memory bitcell;
comparing the predetermined reference current to a drain current generated by the selected non-volatile memory bitcell as the sweeping gate voltage is applied to the selected non-volatile memory bitcell until a transitioning gate voltage is identified; and
outputting a current-voltage curve data point comprising a first value corresponding to the predetermined reference current and a second value corresponding to the transitioning gate voltage.
19. The method of claim 18 , where generating a predetermined reference current comprises:
obtaining a calibration table comprising a plurality of predetermined reference current values and a corresponding plurality of digital values;
selecting a first digital value from the calibration table; and
generating the predetermined reference current corresponding to the selected first digital value.
20. The method of claim 18 , further comprising:
generating a second predetermined reference current;
applying predetermined source and drain voltages to a selected non-volatile memory bitcell;
applying a sweeping gate voltage to the selected non-volatile memory bitcell;
comparing the second predetermined reference current to a drain current generated by the selected non-volatile memory bitcell as the sweeping gate voltage is applied to the selected non-volatile memory bitcell until a second transitioning gate voltage is identified; and
storing the second transitioning gate voltage and second predetermined reference current as current-voltage characteristic information for the selected non-volatile memory bitcell, thereby defining a plurality of current-voltage curve points for the selected non-volatile memory bitcell.
21. The method of claim 20 , further comprising processing the plurality of current-voltage curve points for the selected non-volatile memory bitcell over time to determine if the selected non-volatile memory bitcell a bitcell has bad or impaired transconductance or is otherwise defective.
22. The method of claim 18 , further comprising generating the calibration table by:
setting a digital register setting for a digitally trim-able reference current circuit to a first digital value;
measuring a reference current generated by the digitally trim-able reference current circuit; and
saving the measured reference current and first digital value as a value pair in the calibration table.