Dual die semiconductor package
View Patent ↗A dual die semiconductor package has a grid array of electrical contacts on a bottom surface of a substrate. There is a first semiconductor die with a base surface mounted to an upper surface of the substrate and the first semiconductor die has first die upper surface external electrical connection pads on an upper surface that are electrically connected to respective electrical contacts of the grid array. There is also a second semiconductor die with a base surface mounted to an upper surface of a lead frame flag. There are second die upper surface external electrical connection pads on an upper surface of the second semiconductor die. The dual die semiconductor package includes leads and at least some of the leads are electrically connected to respective pads that provide the second die upper surface external electrical connection pads. A package body at encloses the first semiconductor die and the second semiconductor die. The electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections. Also, at least part of a base surface of the lead frame flag directly under the second semiconductor die is left exposed by the package body and provides a heat sink.
1. A dual die semiconductor package, comprising:
a substrate with a grid array of electrical contacts on a bottom surface thereof;
a first semiconductor die with a base surface mounted to an upper surface of the substrate, the first semiconductor die having a plurality of first die upper surface external electrical connection pads on an upper surface thereof that are electrically connected to respective ones of said electrical contacts of the grid array;
a lead frame including a flag and a plurality of leads;
a second semiconductor die with a base surface mounted to an upper surface of the lead frame flag, the second semiconductor die having second die upper surface external electrical connection pads on an upper surface thereof;
wherein at least one of the leads of the plurality of leads is electrically connected to at least one of said second die upper surface external electrical connection pads;
wherein the substrate is mounted to the lead frame flag, and the lead frame flag has a slot therein for allowing the electrical contacts of the grid array to pass therethrough; and
a package body at least partially enclosing the first semiconductor die and the second semiconductor die, wherein the electrical contacts of the grid array and part of each of the leads protrude from the package body to form external package electrical connections, and wherein at least part of a base surface of the lead frame flag is left exposed by the package body.
2. The dual die semiconductor package of claim 1 , wherein the part of each of the leads that protrudes from the package body forms a seating plane.
3. The dual die semiconductor package of claim 2 , wherein the electrical contacts of the grid array are aligned in the seating plane.
4. The dual die semiconductor package of claim 1 , wherein the part of each of the leads that protrudes from the package body extends from edges of the package body.
5. The dual die semiconductor package of claim 1 , wherein the grid array is a ball grid array.
6. The dual die semiconductor package of claim 1 , wherein at least part of the grid array is aligned directly under the first semiconductor die.
7. The dual die semiconductor package of claim 1 , wherein at least one of the first die upper surface external electrical connection pads is electrically connected to at least one of the leads.
8. The dual die semiconductor package of claim 7 , wherein the at least one of the first die upper surface external electrical connection pads is electrically connected to at least one of said second die upper surface external electrical connection pads.
9. The dual die semiconductor package of claim 1 , wherein at least one of the second die upper surface external electrical connection pads is electrically connected to the lead frame flag.
10. The dual die semiconductor package of claim 9 , further comprising electrical contacts on the base surface of the lead frame flag.
11. The dual die semiconductor package of claim 10 , wherein the electrical contacts on the base surface of the lead frame flag are aligned in the seating plane.