Method and apparatus for decoding received data signals
View Patent ↗Decoding logic is arranged to receive an encoded data signal. The decoding logic comprises a convolutional decoder arranged to perform convolutional decoding on the encoded data signal, to produce a decoded data signal. The decoding logic comprises header bit prediction logic arranged to predict a value for at least one header bit within the decoded data signal, and to provide the predicted value for the at least one header bit to the convolutional decoder to be applied during convolutional decoding.
1. Decoding logic comprising:
a convolutional decoder arranged to receive an encoded data signal and perform convolutional decoding on the encoded data signal to produce a decoded data signal;
a descrambler for descrambling decoded data packets according to a descrambling sequence; and
header bit prediction logic arranged to determine whether the decoded digital signal comprises an inverted synchronization byte, and in response thereto:
predict a value for at least one header bit within the decoded data signal based on statistical analysis of header bit information of previously received encoded data signals;
provide the predicted value for the at least one header bit to the convolutional decoder to be applied during initial convolutional decoding of the encoded data signal;
predict a value for a second header bit based on statistical analysis of header bit information of previously received encoded data signals; and
provide the predicted value for the second header bit to the convolutional decoder to be applied during convolutional decoding, the statistical analysis restricted to statistical analysis of values for headers bits within the header bit information for which no errors are detected.
2. The decoding logic of claim 1 wherein the header bit prediction logic is arranged to predict at least one fixed header bit value.
3. The decoding logic of claim 2 wherein the predicted at least one fixed header bit value comprises at least one of the following fields: synchronization byte;
transport error indicator; transport priority.
4. The decoding logic of claim 2 wherein the header bit prediction logic is further arranged to predict at least one header bit value based on statistical analysis of received header bit information.
5. The decoding logic of claim 1 wherein the statistical analysis of received header bit information comprises performing a bit wise AND comparison of the received header bit information with a comparison string.
6. The decoding logic of claim 5 wherein the at least one header bit value predicted based on statistical analysis comprise at least one of: transport scrambling control; and adaptation field control fields.
7. The decoding logic of claim 1 wherein the at least one header bit value predicted based on statistical analysis comprise at least one of: transport scrambling control; and adaptation field control fields.
8. The decoding logic of claim 7 wherein the descrambler uses a pseudo random binary sequence to descramble the received data packets.
9. The decoding logic of claim 1 further characterised in that the decoding logic further comprises an outer decoder for performing further decoding and error correction on the received data signal.
10. The decoding logic of claim 9 further characterised in that the outer decoder comprises a Reed Solomon decoder.
11. The decoding logic of claim 1 wherein the received encoded data signal comprises an encoded MPEG-2 data signal.
12. The decoding logic of claim 1 wherein the header bit prediction logic is further arranged to predict a value for a third header bit based on statistical analysis of received header bit information and based upon received configuration information on gathering statistical information about header bits, and to provide the predicted value for the third header bit to the convolutional decoder to be applied during convolutional decoding.
13. The decoding logic of claim 1 further comprising a synchronization logic to receive decoded synchronization bytes, the receiving before the descrambling, and to transmit signals to the header bit prediction logic regarding detection of inverted synchronization bytes.
14. A method for decoding a received data signal comprising:
receiving an encoded data signal;
performing at least convolutional decoding on the encoded data signal to produce a decoded data signal;
descrambling decoded data packets according to a descrambling sequence;
determining whether the decoded data signal comprises an inverted synchronization byte; and
in response thereto:
predicting a value for at least one header bit within the decoded data signal based on statistical analysis of header bit information of previously received encoded data signals;
applying the predicted value for the at least one header bit during initial convolutional decoding of the encoded data signal;
predicting a value for a second header bit based on statistical analysis of header bit information of previously received encoded data signals; and
providing the predicted value for the second header bit to the convolutional decoder to be applied during convolutional decoding, the statistical analysis restricted to statistical analysis of values for headers bits within the header bit information for which no errors are detected.
15. The method of claim 14 , wherein the received encoded data signal comprises an encoded MPEG-2 data signal.
16. A semiconductor device comprising:
decoding logic, arranged to receive an encoded data signal, wherein the decoding logic comprises:
a convolutional decoder arranged to perform convolutional decoding on the encoded data signal to produce a decoded data signal;
a descrambler for descrambling decoded data packets according to a descrambling sequence; and
header bit prediction logic arranged to predict a value for a header bit based on statistical analysis of header bit information of previously received encoded data signals, the statistical analysis configurable based upon received configuration information about gathering the header bit information, and to provide the predicted value for the header bit to the convolutional decoder to be applied during convolutional decoding.
17. The semiconductor device of claim 16 , wherein the configuration information specifies a size of a window for collecting information used for the statistical analysis, the size of the window measured by a number of packets.
18. The semiconductor device of claim 16 , wherein the configuration information specifies a window for collecting information used for the statistical analysis, the size of the window based upon a block error rate.