Configurable continuous time sigma delta analog-to-digital converter
View Patent ↗An analog-to-digital converter (ADC) includes a continuous time filter, a quantizer, a continuous time digital-to-analog converter, a discrete time DAC, and a switch. The quantizer has an input terminal coupled to the output terminal of the continuous time filter, and a plurality of output terminals. The continuous time DAC has a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal. The discrete time DAC has a plurality of input terminals coupled to the plurality of output terminals of the quantizer, and an output terminal. The switch has a first input terminal coupled to the output terminal of the continuous time DAC, a second input terminal coupled to the output terminal of the discrete time DAC, and an output terminal coupled to the input terminal of the continuous time filter.
1. An analog-to-digital converter (ADC) comprising:
a continuous time filter having an input terminal and an output terminal;
a quantizer having an input terminal coupled to the output terminal of the continuous time filter, and a multi-bit output;
a continuous time digital-to-analog converter (DAC) having a multi-bit input coupled to the multi-bit output of the quantizer, and an output terminal;
a discrete time DAC having a multi-bit input coupled to the multi-bit output of the quantizer, and an output terminal; and
a switch having a first input terminal coupled to the output terminal of the continuous time DAC, a second input terminal coupled to the output terminal of the discrete time DAC, and an output terminal coupled to the input terminal of the continuous time filter.
2. The ADC of claim 1 , wherein the continuous time filter comprises a plurality of integration stages, and wherein the continuous time filter comprises a plurality of feedforward paths, each feedforward path having an input coupled to one integration stage of the plurality of integration stages, and an output.
3. The ADC of claim 2 , further comprising a summing element, the summing element having a plurality of input terminals, an input terminal of the plurality of input terminals coupled to a feedforward path of the plurality of feedforward paths.
4. The ADC of claim 1 , wherein the continuous time filter is characterized as being one of an RC (resistance-capacitance) filter, an LC (inductance-capacitance) filter, or a gm-C (conductance-capacitance) filter.
5. The ADC of claim 1 , further comprising a delay element coupled between the multi-bit output of the quantizer and the plurality of input terminals of the discrete time DAC.
6. The ADC of claim 1 , wherein the continuous time DAC provides a continuous time DAC pulse.
7. The ADC of claim 1 , wherein the discrete time DAC is characterized as being a switched capacitor DAC.
8. The ADC of claim 1 , further comprising a decimation filter having a multi-bit input coupled to the multi-bit output of the quantizer filter, and a multi-bit output for providing a digital output.
9. The ADC of claim 1 , wherein the continuous time filter is an Nth order integrator, wherein N is an integer greater than or equal to one.
10. An analog-to-digital converter (ADC) comprising:
a filter having an input terminal and a plurality of output terminals;
a summing circuit having a plurality of input terminals coupled to the plurality of output terminals of the filter, and an output terminal;
a quantizer having an input terminal coupled to the output terminal of the summing circuit, and a multi-bit output;
a continuous time digital-to-analog converter (DAC) having a multi-bit input coupled to the multi-bit output of the quantizer, and an output terminal;
a discrete time DAC having a multi-bit input coupled to the multi-bit output of the quantizer, and an output terminal; and
a switch having a first input terminal coupled to the output terminal of the continuous time DAC, a second input terminal coupled to the output terminal of the discrete time DAC, an output terminal coupled to the input terminal of the continuous time filter, and a control terminal for receiving a control signal.
11. The ADC of claim 10 , wherein the filter is an Nth order integrator and N is an integer.
12. The ADC of claim 10 , wherein the filter is a continuous time filter, the continuous time filter characterized as being one of an RC (resistance-capacitance) filter, an LC (inductance-capacitance) filter, or a gm-C (conductance-capacitance) filter.
13. The ADC of claim 10 , further comprising a delay element coupled between the multi-bit output of the quantizer and the plurality of input terminals of the discrete time DAC.
14. The ADC of claim 10 , wherein the continuous time DAC is characterized as being a continuous time return-to-zero DAC.
15. The ADC of claim 10 , wherein the discrete time DAC is characterized as being a switched capacitor DAC.
16. An analog-to-digital converter (ADC) comprising:
a continuous time filter having an input terminal and a plurality of output terminals;
a summing circuit having a plurality of input terminals coupled to the plurality of output terminals of the continuous time filter, and an output terminal;
a quantizer having an input terminal coupled to the output terminal of the summing circuit, and a multi-bit output;
a continuous time digital-to-analog converter (DAC) having a multi-bit input coupled to the multi-bit output of the quantizer, and an output terminal;
a discrete time DAC having a multi-bit input coupled to the multi-bit output of the quantizer, and an output terminal; and
a switch having a first input terminal coupled to the output terminal of the continuous time DAC, a second input terminal coupled to the output terminal of the discrete time DAC, and an output terminal coupled to the input terminal of the continuous time filter, the switch being responsive to a control signal.
17. The ADC of claim 16 , wherein the summing circuit comprises:
a plurality of gain elements, each of the plurality of gain elements having a first input terminal corresponding to an input of the plurality of input terminals of the summing circuit, and the plurality of gain elements each having a second terminal coupled together; and
an amplifier having an input terminal coupled to the second terminals of the plurality of gain elements, and an output terminal coupled to the input terminal of quantizer.
18. The ADC of claim 16 , wherein the continuous time filter is an Nth order integrator, where N is an integer.
19. The ADC of claim 16 , wherein the continuous time DAC is characterized as being a continuous time return-to-zero DAC.
20. The ADC of claim 16 , wherein the discrete time DAC is characterized as being a switched capacitor DAC.