Dual loop phase locked loop with low voltage-controlled oscillator gain
View Patent ↗A dual loop PLL for generating an oscillator signal initially operates in a digital loop to achieve a frequency lock between an input reference signal and a feedback signal and then the PLL operates in an analog loop to achieve a phase lock. After attaining the phase lock, the analog loop is used to maintain the phase lock across frequency and phase variation due to changes in temperature and supply.
1. A Phase Locked Loop (PLL) for generating an oscillator signal, comprising:
a phase-frequency detector (PFD) for generating an analog error signal based on an input reference signal and a feedback signal, wherein the feedback signal is generated using the oscillator signal;
a digital loop, connected to the PFD, for enabling a frequency lock between the input reference signal and the feedback signal, the digital loop comprising:
a time-to-digital converter (TDC), connected to the PFD, for converting the analog error signal to a digital error signal;
a digital filter, connected to the TDC, for generating one or more control words based on the digital error signal; and
a digital-to-analog converter (DAC) current source, connected to the digital filter, for generating a first current corresponding to the one or more control words;
an analog loop, connected to the PFD, for enabling a phase lock between the input reference signal and the feedback signal, the analog loop comprising:
a charge pump, connected to the PFD, for generating a charge pump current based on the analog error signal;
an analog filter, connected to the charge pump, for generating a control voltage based on the charge pump current;
a voltage-to-current converter, connected to the analog filter, for generating a second current based on the control voltage;
a current-controlled oscillator (CCO), connected to the DAC current source and the voltage-to-current converter, for generating the oscillator signal based on at least one of the first current and the second current; and
a frequency divider connected between the CCO and the PFD for generating the feedback signal by adjusting the frequency of the oscillator signal,
wherein the TDC comprises one or more tapped delay lines and a loop feedback counter for converting the analog error signal into the digital error signal, and a thermometric to binary converter for converting one or more thermometric signals generated using the analog error signal into one or more binary signals.
2. The PLL of claim 1 , wherein the PFD generates an UP signal first when the input reference signal leads the feedback signal.
3. The PLL of claim 1 , wherein the PFD generates a DOWN signal first when the input reference signal lags the feedback signal.
4. A system for generating an oscillator signal, comprising:
a phase-frequency detector (PFD) for generating an analog error signal based on an input reference signal and a feedback signal, wherein the feedback signal is generated using the oscillator signal;
a digital loop, connected to the PFD, for enabling a frequency lock between the input reference signal and the feedback signal, the digital loop comprising:
a time-to-digital converter (TDC), connected to the PFD, for converting the analog error signal to a digital error signal;
a digital filter, connected to the TDC, for generating one or more control words using the digital error signal; and
a digital-to-analog converter (DAC) current source, connected to the digital filter, for generating a first current corresponding to the one or more control words;
an analog loop, connected to the PFD, for enabling a phase lock between the input reference signal and the feedback signal, the analog loop comprising:
a charge pump, connected to the PFD, for generating a charge pump current based on the analog error signal;
an analog filter, connected to the charge pump, for generating a control voltage based on the charge pump current; and
a voltage-to-current converter, connected to the analog filter, for generating a second current based on the control voltage; and
a current-controlled oscillator (CCO), connected to the DAC current source and the voltage-to-current converter, for generating the oscillator signal based on at least one of the first current and the second current,
wherein the TDC comprises one or more tapped delay lines and a loop feedback counter for converting the analog error signal to the digital error signal, and a thermometric to binary converter for converting one or more thermometric signals generated using the analog error signal into one or more binary signals.
5. The system for generating an oscillator signal of claim 4 , further comprising a frequency divider connected between the CCO and the PFD for adjusting the frequency of the oscillator signal to generate the feedback signal.
6. The system for generating an oscillator signal of claim 4 , wherein the PFD generates an UP signal first when the input reference signal leads the feedback signal.
7. The system for generating an oscillator signal of claim 4 , wherein the PFD generates a DOWN signal first when the input reference signal lags the feedback signal.