Clock glitch detection circuit
View Patent ↗In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.
1. A circuit for detecting clock glitches in a clock signal, comprising
a master counter clocked by the clock signal configured to store a master count N M ;
an incrementer configured to advance the master count by one increment;
a slave counter clocked by the clock signal configured to store a slave count N s , wherein
the slave count is retarded relative to the master count by at least P clock edges based on an input of the slave counter being coupled to an output of the master counter, and
the number P is greater than or equal to one; and
a comparator configured to determine whether a difference N M −N S between the master count and the slave count is at least P times the increment.
2. The circuit as set forth in claim 1 , wherein the comparator or its result is activated by the clock signal.
3. The circuit as set forth in claim 1 , wherein the incrementer is combinatorial.
4. The circuit as set forth in claim 1 , wherein the master counter and the slave counter comprise wraparound counters having the same range.
5. The circuit as set forth in claim 1 , wherein the master counter comprises a master storage element configured to store the master count and the slave counter comprises a slave storage element configured to store the slave count.
6. The circuit as set forth in claim 1 , wherein a slave count capture time is shorter than a delay of the incrementer.
7. The circuit as set forth in claim 1 , wherein
the master counter comprises a master input port for setting the master count and a master output port for delivering the master count, and
the slave counter comprises a slave input port for setting the slave count and a slave output port for delivering the slave count.
8. The circuit as set forth in claim 7 , wherein the output of the master counter is coupled directly to the input of the slave counter.
9. The circuit as set forth in claim 3 , wherein the incrementer comprises:
an incrementer input port for receiving an input number; and
an incrementer output port for delivering an output number, wherein
the output number is the input number advanced by one increment, and
the output of the master counter is coupled to the incrementer input port and the incrementer output port is coupled to an input port of the master counter.
10. The circuit as set forth in claim 9 , wherein the comparator comprises:
a first comparator input port for receiving a first input number;
a second comparator input port for receiving a second input number; and
a comparator output port for delivering a comparator signal depending on the difference between the first input number and the second input number, wherein
the output of the master counter is coupled to the first comparator input port and an output of the slave counter is coupled to the second comparator input port.
11. The circuit as set forth in claim 1 , wherein the master counter, the incrementer, the slave counter, and the comparator represent a first instance that is arranged to store positive clock edges, wherein circuit further comprises:
a second master counter clocked by the clock signal configured to store a second master count;
a second incremmter configured to advance the second master count by one increment;
a second slave counter clocked by the clock signal configured to store a second slave count, wherein the second slave count is retarded relative to the second master count by at least P clock edges based on an input of the second slave counter being coupled to an output of the second master counter, and wherein the number P is greater than or equal to one; and
a second comparator configured to determine whether the difference between the second master count and the second slave count is at least P times the increment, wherein the second master counter, the second incrementer, the second slave counter, and the second comparator represent a second instance arranged to store negative clock edges, and circuit further comprises a third comparator determines a difference between rising-edge count and falling-edge count is provided.
12. A method for detecting clock glitches in a clock signal, comprising:
storing a master count N M at a master counter clocked by the clock signal;
advancing the master count by one increment;
storing a slave count N S at a slave counter clocked by the clock signal, wherein
the slave count is retarded relative to the master count by at least P clock edges based on an input of the slave counter being coupled to an output of the master counter, and
the number P is greater than or equal to one; and
determining whether a difference N M −N S between the master count and the slave count is at least P times the increment.
13. The method of claim 12 , wherein the master counter and the slave counter comprise wraparound counters having the same range.
14. The method of claim 12 , wherein the output of the master counter is coupled directly to the input of the slave counter.
15. The method of claim 12 , further comprising:
activating a comparator by the clock signal to determine the difference between the master count and the slave count.
16. A circuit for detecting clock glitches in a clock signal, comprising
a master counter clocked by the clock signal configured to store a master count N M ;
an incrementer configured to advance the master count by one increment, wherein the incrementer includes:
an incrementer input port to receive an input number; and
an incrementer output port to deliver an output number, wherein the output number is the input number advanced by one increment, and an output of the master counter is coupled to the incrementer input port and the incrementer output port is coupled to an input port of the master counter;
a slave counter clocked by the clock signal configured to store a slave count N S , wherein the slave count is retarded relative to the master count by at least P clock edges based on an input of the slave counter being coupled to the output of the master counter, and the number P is greater than or equal to one; and
a comparator configured to determine whether a difference N M −N s between the master count and the slave count is at least P times the increment.
17. The circuit of claim 16 , wherein the comparator comprises:
a first comparator input port for receiving a first input number;
a second comparator input port for receiving a second input number; and
a comparator output port for delivering a comparator signal depending on the difference between the first input number and the second input number, wherein the output of the master counter is coupled to the first comparator input port and an output of the slave counter is coupled to the second comparator input port.
18. The circuit of claim 16 , wherein the master counter and the slave counter comprise wraparound counters having the same range.
19. The circuit of claim 16 , wherein the output of the master counter is coupled directly to the input of the slave counter.
20. The circuit of claim 16 , wherein the comparator or its result is activated by the clock signal.