Multi-processor data processing system having synchronized exit from debug mode and method therefor
View Patent ↗A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.
1. A data processing system comprising:
a plurality of data processors;
debug logic coupled to each data processor of the plurality of data processors, the debug logic for providing an instruction for exiting debug mode to the plurality of data processors; and
linking logic, coupled to the debug logic and to each of the plurality of data processors, the linking logic for linking selected ones of the plurality of data processors with each other and to the debug logic, wherein the debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic, and
wherein each of the plurality of data processors comprises an output terminal for providing an exit debug signal in response to receiving the instruction for exiting the debug mode.
2. The data processing system of claim 1 , wherein each of the plurality of data processors comprises an individual test access port (TAP) controller in accordance with IEEE (Institute of Electrical and Electronics Engineers) standard 1149.1 (JTAG (Joint Test Action Group)).
3. The data processing system of claim 2 , wherein the debug logic comprises a top-level test access port (TAP) controller, and wherein the individual TAP controllers of the selected ones of the plurality of data processors are linked in parallel with each other and to the top-level TAP controller.
4. The data processing system of claim 1 , wherein each of the plurality of data processors provides the exit debug signal in response to receiving the instruction for exiting the debug mode regardless of whether or not each of the plurality of data processors is in debug mode.
5. The data processing system of claim 1 , wherein each of the plurality of data processors that are not in debug mode treat the instruction for exiting the debug mode as a no operation (NOP) instruction.
6. The data processing system of claim 1 , further comprising a logic gate having a plurality of input terminals for receiving the exit debug signals from the plurality of data processors, the logic gate having an output terminal for providing a hardware exit debug signal to a plurality of modules.
7. A data processing system comprising:
a plurality of data processors;
debug logic coupled to each data processor of the plurality of data processors, the debug logic for providing an instruction for exiting debug mode to the plurality of data processors;
linking logic, coupled to the debug logic and to each of the plurality of data processors, the linking logic for linking selected ones of the plurality of data processors with each other and to the debug logic, wherein the debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic; and
combinational logic having a plurality of inputs and an output, wherein the plurality of data processors each provide an exit debug signal to a selected input of the plurality of inputs, and in response, the combinational logic providing a hardware exit debug signal at the output.
8. The data processing system of claim 7 , further comprising a plurality of modules, each of the plurality of modules having an input for receiving the hardware exit debug signal.
9. A method for exiting debug mode in a data processing system having a plurality of data processors, the method comprising:
providing an exit debug instruction to each processor of the plurality of data processors;
determining that a first processor of the plurality of data processors is in a debug mode;
causing the first processor to exit debug mode and begin normal instruction execution;
determining that a second processor of the plurality of data processors is not in the debug mode;
causing the second processor to treat the exit debug instruction as a no operation (NOP) instruction; and
causing each processor of the plurality of processors to provide an exit debug signal.
10. The method of claim 9 , wherein providing an exit debug instruction to each processor of the plurality of processors further comprises providing the exit debug instruction to the plurality of processors in parallel.
11. The method of claim 9 , further comprising providing a hardware exit debug signal to a plurality of modules in response to the exit debug signal provided by each of the plurality of processors.
12. The method of claim 9 , further comprising linking an individual test access port (TAP) of each processor of the plurality of processors in parallel with each other and to a top-level TAP controller of the data processing system prior to providing the exit debug instruction to each processor of the plurality of data processors.
13. The method of claim 9 , further comprising:
providing the exit debug signal from each processor of the plurality of processors to a corresponding input of combinational logic having a plurality of inputs; and
providing a hardware exit debug signal from an output of the combinational logic to each module of a plurality of modules.
14. The method of claim 9 , wherein providing an exit debug instruction to each processor of the plurality of data processors further comprises scanning the exit debug instruction to the plurality of processors as a JTAG (Joint Test Action Group) command.
15. A method for exiting debug mode in a data processing system having a plurality of processors, the method comprising:
linking a test access port (TAP) of each processor of the plurality of processors in parallel with each other and to a top-level TAP controller of the data processing system;
providing an exit debug instruction to each processor of the plurality of processors via the TAP of each processor; and
providing a hardware exit debug signal from each processor of the plurality of processors to cause a plurality of modules to exit the debug mode.
16. The method of claim 15 , further comprising:
determining that a first processor of the plurality of data processors is in a debug mode; and
causing the first processor to exit debug mode and begin normal instruction execution.
17. A method for exiting debug mode in a data processing system having a plurality of processors, the method comprising:
linking a test access port (TAP) of each processor of the plurality of processors in parallel with each other and to a top-level TAP controller of the data processing system;
providing an exit debug instruction to each processor of the plurality of processors via the TAP of each processor;
determining that a second processor of the plurality of data processors is not in the debug mode; and
causing the second processor to treat the exit debug instruction as a no operation (NOP) instruction.
18. The method of claim 17 further comprising:
each processor of the plurality of processors generating an exit debug signal in response to receiving the exit debug instruction;
providing the exit debug signal from each processor of the plurality of processors to a corresponding input of combinational logic having a plurality of inputs; and
providing a hardware exit debug signal from an output of the combinational logic to each module of a plurality of modules.