FAULT DETECTION APPARATUS FOR ALPHANUMERIC DISPLAY SYSTEM AND METHOD OF DETECTING A FAULT
A fault detection apparatus comprises a signal translation stage having an input arranged to receive an input waveform derived from a signal for a capacitive load. The signal translation stage is arranged to generate a translated output signal representative of at least an aspect of the input waveform. The apparatus also comprises a detection stage arranged to receive the translated output signal from the signal translation stage and analyse a first part and a second part of the translated output signal respectively corresponding to a first step function and a second step function, the first and second step functions being opposite in direction of transition. The analysis performed by the detection stage is a comparison of the first and second parts of the translated output signal respectively with an expected first part and an expected second part of the translated output signal.
1 . A fault detection apparatus comprising:
a signal translation stage having an input arranged to receive an input waveform derived, when in use, from a signal for driving a capacitive load, the signal translation stage being arranged to generate a translated output signal representative of at least an aspect of the input waveform; and
a detection stage arranged to receive the translated output signal from the signal translation stage and analyse a first part of the translated output signal corresponding to a first step function and identify first detected bits constituting the first part of the translated output signal;
wherein the analysis performed by the detection stage is a comparison of the first part of the translated output signal with an expected first part of the translated output signal.
2 . An apparatus as claimed in claim 1 , wherein the input waveform is an analogue signal and the signal translation stage is arranged to digitise the input waveform, the digitised input waveform constituting the translated output signal.
3 . An apparatus as claimed in claim 2 , wherein the translated output signal comprises a bit, the bit having a state corresponding to one of: logic 1 or logic 0.
4 . An apparatus as claimed in claim 3 , wherein the signal translation stage comprises a slicer.
5 . An apparatus as claimed in claim 1 , wherein the detection stage is arranged to sum the first detected bits to yield a first measured value.
6 . An apparatus as claimed in claim 5 , wherein:
a first expected value corresponds to a sum of bits of a first expected bit pattern, the first expected bit pattern constitutes the expected first part of the translated output signal; and
the comparison between the first part of the translated output signal and the expected first part of the translated output signal is a comparison of the first measured value with the first expected value.
7 . An apparatus as claimed in claim 2 , wherein the translated output signal comprises a bit, the bit having a state corresponding to one of: logic 1, logic 0, or an indeterminate state.
8 . An apparatus as claimed in claim 7 , wherein:
a first expected bit pattern constitutes the expected first part of the translated output signal;
the detection stage is arranged to identify first detected bits constituting the first part of the translated output signal; and
the detection stage is also arranged to make a bit position-by-bit position comparison of the first detected bits with the first expected bit pattern.
9 . An apparatus as claimed in claim 8 , wherein the first detected bits comprise a first detected bit at a first bit position and the first expected bit pattern comprises a first expected bit at a bit position corresponding to the first bit position, the detection stage being arranged to determine a mismatch between the first detected bit and the first expected bit, the mismatch being indicative of a fault condition.
10 . An apparatus as claimed in claim 9 , wherein the first expected bit is of a first indeterminate state, the comparison discounting any mismatch between the state of the first expected bit and a state of the first detected bit.
11 . An apparatus as claimed in claim 1 , wherein the signal translation stage comprises a multi-state transformer.
12 . An apparatus as claimed in claim 1 , wherein the signal translation stage is arranged to generate at least part of a spectrum associated with the input waveform.
13 . An apparatus as claimed in claim 12 , wherein the first part of the translated output signal is a first part of the spectrum associated with the first step function.
14 . An apparatus as claimed in claim 1 , wherein a mismatch between the first part of the translated output signal and the respective expected first part of the translated output signal is indicative of a fault condition.
15 . An apparatus as claimed in claim 1 , wherein the capacitive load is a segment of a display device.
16 . An apparatus as claimed in claim 1 , wherein the detection stage is arranged to receive the translated output signal from the signal translation stage and analyse a second part of the translated output signal corresponding to a second step function, a direction of transition of the second step function being opposite to a direction of transition of the first step function; and
the analysis performed by the detection stage includes a comparison of the second part of the translated output signal with an expected second part of the translated output signal.
17 . (canceled)
18 . An electronic apparatus comprising the fault detection apparatus as claimed in claim 1 .
19 . (canceled)
20 . A method of detecting a fault for a capacitive load, the method comprising:
receiving an input waveform tapped from a signal for driving the capacitive load;
generating a translated output signal representative of at least an aspect of the input waveform;
analysing a first part of the translated output signal corresponding to a first step function and identifying first detected bits constituting the first part of the translated output signal; wherein
the analysis performed is a comparison of the first part of the translated output signal with an expected first part of the translated output signal.
21 . A non-transitory computer readable storage medium comprising computer program code means to make a computer execute the method as claimed in claim 20 .
22 . (canceled)
23 . An electronic apparatus as claimed in claim 18 , further comprising:
a display device comprising a display segment; and
a display driver coupled to the display segment;
wherein the input of the signal translation stage is coupled to a tap for receiving the input waveform, the tap being coupled to the display segment and the display driver.