Sigma-delta modulator apparatus and method of generating a modulated output signal
View Patent ↗A discrete time sigma-delta modulator apparatus for class-D operation comprises a feed-forward path having an input at one end thereof and an output at another end thereof. A first summation unit is coupled in the feed-forward path to a first integrator. A quantizer is coupled in the feed-forward path after the first integrator and a feedback path arrangement is coupled to an input of the first summation unit. A low pass filter is arranged in the feedback path arrangement so as only to drive the first integrator.
1. A discrete time sigma-delta modulator apparatus for class-D operation, the apparatus comprising:
a feed-forward path having an input at one end thereof and an output at another end thereof;
a first summation unit coupled in the feed-forward path to a first switched capacitor integrator;
a quantizer coupled in the feed-forward path after the first switched capacitor integrator;
a feedback path coupled to an input terminal of the first summation unit;
a low pass filter having an input terminal coupled to an output terminal of the quantizer, and an output terminal coupled to a load via the output of the feed-forward path and to the input terminal of the first summation unit via the feedback path; and
wherein the apparatus has a modulator running frequency;
wherein the low pass filter has a cut-off frequency, the cut-off frequency of the low pass filter being less than the modulator running frequency.
2. An apparatus as claimed in claim 1 , further comprising:
a second integrator coupled to the first integrator in the feed forward path via a second summation unit;
wherein the quantizer is coupled in the feed forward path to an output of the second integrator; and
wherein the feedback path arrangement is also coupled to an output of the second summation unit.
3. An apparatus as claimed in claim 2 , wherein a second feedback path extends from the output terminal of the quantizer to an input terminal of the second summation unit.
4. An apparatus as claimed in claim 2 , wherein:
the input of the feed-forward path is coupled to another input of the first summation unit, an output of the first summation unit being coupled to an input of the first integrator;
an output of the first integrator is coupled to another input of the second summation unit, an output of the second summation unit being coupled to an input of the second integrator; and
the output of the second integrator is coupled to an input of the quantizer.
5. An apparatus as claimed in claim 2 , wherein:
the output terminal of the quantizer is coupled to an input terminal of the second summation unit.
6. An apparatus as claimed in claim 1 , wherein the low pass filter is an RC circuit.
7. An apparatus as claimed in claim 1 , wherein the low pass filter is an LC circuit.
8. A semiconductor device comprising the amplifier circuit apparatus as claimed in claim 7 .
9. An apparatus as claimed in claim 1 , wherein the apparatus has a noise transfer function having a pole, the pole having a negative real part.
10. An apparatus as claimed in claim 9 , wherein:
the input of the feed-forward path is coupled to another input of the first summation unit, an output of the first summation unit being coupled to an input of the first integrator;
an output of the first integrator is coupled to another input of the second summation unit, an output of the second summation unit being coupled to an input of the second integrator; and
the output of the second integrator is coupled to an input of the quantizer.
11. An apparatus as claimed in claim 1 , wherein the low pass filter is a passive filter.
12. An amplifier circuit apparatus comprising:
the discrete time sigma-delta modulator apparatus as claimed in claim 1 ; and
an output driver coupled between the output terminal of the quantizer and the output of the feed-forward path.
13. An apparatus as claimed in claim 12 , wherein a second feedback path extends from an output of the output driver to an input terminal of a second summation unit.
14. An apparatus as claimed in claim 13 , wherein:
an output of the output driver is coupled to the input terminal of the first summation unit; and
the output of the output driver is coupled to the input terminal of the first summation unit via the low pass filter.
15. An apparatus as claimed in claim 14 , wherein the output of the output driver and the input terminal of the second summation unit are coupled to the input terminal of the low pass filter.
16. A semiconductor device comprising the amplifier circuit apparatus as claimed in claim 13 .
17. An apparatus as claimed in claim 12 , wherein:
the output terminal of the quantizer is coupled to the input terminal of the second summation unit.
18. A semiconductor device comprising the discrete time sigma-delta modulator apparatus as claimed in claim 1 .
19. A method of generating a modulated output signal, the method comprising:
receiving an input signal;
providing a feed-forward path having an input and an output, the feed-forward path being provided by:
a first summation unit coupled to a first switched capacitor integrator, the first switched capacitor integrator being coupled to a quantizer;
applying the input signal to the feed-forward path so as to provide the modulated output signal at the output of the feed-forward path; and
a modulator running frequency;
feeding back a portion of the modulated output signal to an input of the first summation unit only; and
low pass filtering the portion of the modulated output signal fed back to the input of the first summation unit, the low pass filtering being with respect to a cut-off frequency less than the modulator running frequency.
20. A discrete time sigma-delta modulator apparatus for class-D operation, the apparatus comprising:
a feed-forward path between an input terminal and an output terminal of the apparatus;
a summation unit coupled in the feed-forward path, the summation unit having an input terminal coupled to the input terminal of the apparatus, and an output terminal coupled to an input terminal of a switched capacitor integrator;
a quantizer coupled in the feed-forward path, the quantizer having an input terminal coupled to an output terminal of the switched capacitor integrator, and an output terminal;
a drive circuit coupled having an input terminal coupled to the output terminal of the quantizer, and an output terminal coupled to a load;
a low pass filter in a feed-back path, the low pass filter having an input terminal coupled to the input terminal of the drive circuit, and an output terminal; and
a feedback path coupled between the output terminal of the quantizer and the input terminal of the summation unit, wherein the apparatus has a modulator running frequency, and wherein the low pass filter has a cut-off frequency, the cut-off frequency of the low pass filter being less than the modulator running frequency.