Program trace message generation for page crossing events for debug
View Patent ↗A data processing system has a trace message filtering circuit. A method includes: receiving a current page address corresponding to a current instruction in a sequence of instructions; determining that the current page address is for a different page of memory than a previous page address corresponding to a previous instruction in the sequence of instructions; comparing the current page address with a plurality of page addresses stored in a message filtering circuit; and when the current page address is determined to be different than any of the plurality of page addresses, storing the current page address in the message filtering circuit.
1. A method comprising:
receiving a current page address corresponding to a current instruction in a sequence of instructions;
determining that the current page address is for a different page of memory than a previous page address corresponding to a previous instruction in the sequence of instructions;
comparing the current page address with a plurality of page addresses stored in a message filtering circuit; and
when the current page address is determined to be different than any of the plurality of page addresses, storing the current page address in the message filtering circuit.
2. The method of claim 1 , wherein the current page address and the previous page address are both virtual page addresses.
3. The method of claim 2 , further comprising generating a trace message for providing physical address information, the physical address information corresponding to the current virtual page address.
4. The method of claim 3 , wherein the trace message is conditionally generated based upon a result of comparing the current page address with one or more of the plurality of page addresses.
5. The method of claim 1 , wherein determining that the current page address is for the different page of memory further comprises determining that the current page address is for a page of the memory that is not adjacent to a page addressed by the previous page address.
6. The method of claim 5 , wherein determining that the current page address is for the page of the memory that is not adjacent to the page addressed by the previous page address further comprises determining that a current physical page address is for a page of the memory that is not adjacent to a page addressed by a previous physical address.
7. The method of claim 1 , wherein storing the current page address in the message filtering circuit further comprises storing the current page address in a first-in, first-out buffer of the message filtering circuit.
8. The method of claim 1 , wherein the method is performed during normal operation of a data processing system for real-time debugging of the data processing system.
9. A method comprising:
receiving a current virtual page address corresponding to a current instruction in a sequence of instructions;
determining that the current virtual page address is for a different page of memory than a previous virtual page address corresponding to a previous instruction in the sequence of instructions;
comparing the current virtual page address with each of a plurality of virtual page addresses stored in a message filtering circuit;
when the current virtual page address is determined to be different than any of the plurality of virtual page addresses storing the current virtual page address in the message filtering circuit; and
generating a trace message for providing physical address information corresponding to the current virtual page address.
10. The method of claim 9 , wherein determining that the current virtual page address is for a different page of memory than the previous virtual page address further comprises determining that a physical page boundary is crossed.
11. The method of claim 10 , wherein determining that a physical page boundary is crossed further comprises determining that the physical page boundary is crossed from a first physical page to a second physical page.
12. The method of claim 11 , wherein the second physical page is not adjacent to the first physical page.
13. The method of claim 9 , wherein storing the current virtual page address further comprises storing the current virtual page address in a first-in, first-out buffer of the message filtering circuit.
14. The method of claim 9 , wherein the method is performed during normal operation of a data processing system for read-time debugging of the data processing system.
15. A data processing system comprising:
a memory organized as a plurality of pages;
an instruction fetch unit for fetching a sequence of instructions, the sequence of instructions having corresponding addresses;
an execution unit for executing the sequence of instructions; and
a debug unit comprising:
a page crossing detection circuit for receiving the addresses in the sequence, and for determining when a page boundary in the memory is crossed from a first page to a second page;
a message filtering circuit, comprising:
a storage unit for storing a plurality of page addresses;
a comparator for comparing an address of the second page to each of the plurality of page addresses, and for providing an output to indicate when the address of the second page is different from each of the plurality of page addresses; and
a control circuit for causing the address of the second page to be stored in the storage unit when the output is provided by the comparator.
16. The data processing system of claim 15 , further comprising trace message generating circuitry, the trace message generating circuit for providing physical address information corresponding to the address of the second page.
17. The data processing system of claim 15 , wherein the storage unit is a first-in, first-out buffer.
18. The data processing system of claim 15 , wherein the first page is not adjacent to the second page.
19. The data processing system of claim 15 , wherein the comparator is for comparing virtual page addresses.
20. The data processing system of claim 15 , wherein the debug unit is for real-time debugging of the data processing system during a normal operating mode.