Granted Patent B2

US 8,401,019 · App. 12/738,421 · Granted Mar 19, 2013

Abstract

Claims (48)

1. A method of scheduling a processing of frames of packet stream channels at a gateway, a frame comprising a plurality of packets, the method comprising:

determining whether at least one packet stream channel comprises a frame ready for processing;

if at least one packet stream channel comprises a frame ready for processing, identifying a frame ready for processing that has a highest priority; and scheduling the identified highest priority frame for processing, wherein:

a frame at the gateway is not ready for processing until arrival at the gateway of a packet that completes the frame; and

prioritising a frame of a packet stream channel ready for processing is based on at least:

a frame availability time;

an estimated processing time for the frame; and

a number of times wherein frames of the packet stream channel have been processed in urgent mode.

2. The method of claim 1 further characterised by computing a frame availability time of a frame ready for processing as an oldest arrival time of a data packet that completes the frame ready for processing.

3. The method of claim 1 further characterised in that prioritising a frame comprises calculating a difference between the frame availability time and a current time, minus an estimation of a length of time required to process the frame.

4. The method of claim 1 further characterised by prior to scheduling a frame for processing, estimating a latency of that frame, and if the latency of the frame exceeds a latency threshold, processing the frame with a higher priority.

5. The method of claim 1 further characterised in that frames ready for processing are further prioritised based on at least one of:

(i) channel history for those frames,

(ii) a data content for those frames,

(iii) a frame type for those frames;

(iv) a frequency with which frames within a channel are processed with a higher priority.

6. The method of claim 1 further characterised in that determining whether at least one packet stream channel comprises a frame ready for processing comprises polling a plurality of channel buffers to obtain a status of the at least one packet channel frame.

7. The method of claim 1 , wherein prioritising a frame of a packet stream channel is further based in part upon the formula:

P f =frame_delay−channel_processing_length+urgent_cnt+Δ frame-type

wherein frame_delay is a measure of a difference between the frame availability time and a current time, channel_processing_length is an estimation of a length of time required to process the frame, urgent_cnt is a number of times wherein frames of the packet stream channel have been processed in urgent mode, and Δ frame-type is a representation of a frame type.

8. The method of claim 1 , wherein processing a frame in urgent mode comprises running a decoder part of a transcoder and not running an encoder part of the transcoder.

9. The method of claim 1 , further comprising:

determining that a waiting time for a frame to become complete has expired; and

scheduling the frame based upon a time at which the waiting time has expired.

10. The method of claim 1 , further comprising processing the frame, wherein the processing comprises at least one of the following:

changing an encoding of the frame from one standard to another;

changing a frame rate for an input media stream;

changing a bit rate for an input media stream; and

changing a frame size of an input media stream.

11. The method of claim 1 , further comprising processing a frame of the frames of the packet stream channel in urgent mode based upon a latency of the frame exceeding a latency threshold for the frame.

12. An Integrated Circuit for scheduling a processing of packet stream channels, wherein the integrated circuit comprises:

logic for determining whether at least one packet stream channel comprises a frame ready for processing, wherein a frame comprises a plurality of packets and a frame is not ready for processing until arrival at the Integrated Circuit of a packet that completes the frame and if at least one packet stream channel comprises a frame ready for processing, identifying a frame ready for processing that has a highest priority; and

scheduler logic operably coupled to the logic for determining and arranging to schedule the identified highest priority frame for processing;

wherein the scheduler logic is arranged to prioritise a frame of a packet stream channel ready for processing based on at least: a frame availability time; an estimated processing time for the frame; and a number of times wherein frames of the packet stream channel have been processed in urgent mode.

13. The Integrated Circuit of claim 12 further characterised in that the scheduler logic is arranged to compute the frame availability time of a frame ready for processing as an oldest arrival time of a data packet that completes the frame ready for processing.

14. The Integrated Circuit of claim 12 further characterised in that the scheduler logic is arranged to prioritise a frame ready for processing by calculating a difference between the frame availability time and a current time, minus an estimation of a length of time to process the frame.

15. The Integrated Circuit of claim 12 further characterised in that the scheduler logic is arranged to, prior to scheduling a frame, estimate a latency of that frame, and if the latency of the frame exceeds a latency threshold, process the frame with a higher priority.

16. The Integrated Circuit of claim 12 further characterised by the scheduler logic is arranged to further prioritise frames ready for processing based on at least one of:

(i) channel history for those frames,

(ii) a data content for those frames,

(iii) a frame type for those frames,

(iv) a frequency with which frames within a channel are processed with a higher priority.

17. The Integrated Circuit of claim 12 further characterised by the Integrated Circuit further comprising a plurality of channel buffers arranged to receive and store data packets; wherein the scheduler logic is arranged to determine whether at least one packet stream channel comprises a frame ready for processing by polling the plurality of channel buffers to obtain a status of the at least one packet channel frame.

18. A communication unit comprising the integrated circuit of claim 12 .

19. A non-transitory computer-readable storage element having computer-readable code stored thereon for programming a computer to perform a method of scheduling a processing of packet stream channels, the method comprising:

determining whether at least one packet stream channel comprises a frame ready for processing, wherein a frame comprises a plurality of packets and a frame is not ready for processing until arrival of a packet that completes the frame at a computer, wherein the computer contains the non-transitory computer-readable storage element; and if at least one packet stream channel comprises a frame ready for processing, identifying a frame ready for processing that has a highest priority; and scheduling the identified highest priority frame;

wherein prioritising a frame of a packet stream channel ready for processing is based on at least a frame availability time, an estimated processing time for the frame, and a number of times wherein frames of the packet stream channel have been processed in urgent mode.

20. The computer-readable storage element of claim 19 further characterised by the computer-readable storage element comprising at least one of a hard disk, a CD-ROM, an optical storage device, a magnetic storage device, a ROM (Read Only Memory), a PROM (Programmable Read Only Memory), a EPROM (Erasable Programmable Read Only Memory), a EEPROM (Electronically Erasable Programmable Read Only Memory and a Flash memory.

Assignments (26)