Granted Patent B2

US 8,458,447 · App. 13/162,835 · Granted Jun 4, 2013

Abstract

Claims (55)

1. A data processor comprising:

a branch target buffer (BTB) including a plurality of BTB entries grouped in ways, wherein the BTB entries in one of the ways include a short tag address and the BTB entries in another one of the ways include a full tag address; and

a page address buffer that includes entries for page address portions of a plurality of previously-received branch instructions in relation to the short tag address;

wherein the entries in the BTB that include the short tag address further include a select field that is used to select one of the entries in a page address buffer.

2. The processor of claim 1 , further comprising:

the BTB entries in one of the ways include a short target address and the BTB entries in another one of the ways include a full target address.

3. The processor of claim 1 , further comprising:

a control and interface unit configured to:

keep track of a number of branch instruction entries allocated in the BTB that are on the same page;

maintain a same page status counter to indicate a number of the previously-received branch instructions that were on the same page;

wherein the BTB allocates an entry in a page address buffer if an entry is not already in the page address buffer when the number of branch instruction entries reaches a threshold number.

4. The processor of claim 1 , further comprising,

the BTB entries include a short target address;

a page target address buffer that includes entries for page address portions of a plurality of previously-received target addresses of branch instructions; and

the BTB entries include a target select field that is used to select one of the entries in the page target address buffer.

5. The processor of claim 2 , wherein:

the BTB is configured to:

for the short target address, concatenate a page address portion of a current branch instruction having a same page address with a selected short target address to determine a branch target address for the instruction.

6. The processor of claim 4 , wherein the BTB is configured to:

concatenate a page address portion of a current branch instruction or previously-received page address portion from the page target address buffer having a same page address with a selected short target address to determine a branch target address for the current branch instruction.

7. A data processor comprising:

a set associative branch target buffer (BTB) array including sets of BTB entries grouped in ways, wherein the BTB entries in the sets of a first one of the ways include a short tag address field and the BTB entries in the sets of a second one of the ways include a full tag address field;

a first comparator configured to receive a short tag address from an incoming instruction and a short tag address from a selected set in the ways that include the short tag address field, the comparator is further configured to output a short way tag match signal that indicates whether the short tag address from the incoming instruction was equal to one of the short tags from the selected set in the ways that include the short tag address field;

a page address buffer configured to store entries that include page addresses from previously received instruction addresses; and

a match indicator select unit configured to receive the entries from the page address buffer and the select field from the selected set in the ways that include the short tag address field; and

wherein the BTB entries in the sets of the first one of the ways include a select field that indicates an entry in a page address buffer for the selected set.

8. The processor of claim 7 , further comprising:

a control and interface unit configured to:

maintain a same page status counter to indicate a number of branch instructions that are on a same page; and

a page address buffer that includes page address entries for the branch instructions that are on the same page.

9. The processor of claim 7 , wherein the number of bits allotted for the short tag address field is one of the group consisting of: less than the number of bits allotted for the full tag address field, and based on a page address of a memory management unit (MMU).

10. The processor of claim 7 , further comprising:

a second comparator configured to receive a full tag address from the incoming instruction and a full tag address from the selected set in the ways that include the full tag address field, the second comparator is further configured to output a long hit way signal indicating whether the full tag address from the incoming instruction was equal to one of the full tag addresses from the selected set in the ways that include the full tag address field.

11. The processor of claim 7 , further comprising:

a logic circuit configured to receive a short way tag match signal from the first comparator and a way page match signal from the match indicator select unit, the logic circuit is further configured to output a short hit way signal indicating whether the page address of the incoming instruction address is already present in the page address buffer.

12. In a processor having a branch target buffer (BTB) including sets of BTB entries grouped in ways, a method comprising:

receiving a branch instruction address;

using an index portion of the instruction address to select one of the sets, wherein the BTB entries in the sets of a first group of the ways include a short tag address portion and the BTB entries in the sets of a second group of the ways include a full tag address portion; and

for the first group of the ways,

determining whether the short tag address portions in the selected set match a tag portion of the branch instruction address;

generating page address match indicators by comparing a page address portion of the instruction address to entries in a page address buffer, wherein the entries in the page address buffer include page addresses from previously-received instruction addresses; and

generating way page matches from the page address match indicators based on select fields of the selected set.

13. The method of claim 12 , further comprising:

for the first group of the ways,

generating hit way signals based on the way tag matches and way page matches; and

generating a way branch target address by concatenating the page address portion of the instruction address with a target address of the selected set.

14. The method of claim 12 , further comprising:

keeping track of a number of branch instruction entries allocated in the BTB that are on the same page; and

allocating an entry in a page address buffer if an entry is not already in the page address buffer when the number of branch instruction entries reaches a threshold number.

15. The method of claim 14 , further comprising:

for the second group of the ways,

generating hit way signals for the selected set by determining whether a page address portion and a tag portion of the instruction address is equal to the full tag address portion of the selected set; and

providing a target address of the selected set as a way branch target address.

16. The method of claim 15 , further comprising:

providing a same page indicator and prediction information with the way branch target address to the processor.

Assignments (24)