DC compensation for VLIF signals
View Patent ↗Receiver circuitry for processing a received Very Low Intermediate Frequency signal wherein the receiver circuitry comprises a main processing path. The main processing path comprises mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal. The receiver circuitry further comprises a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal. The receiver circuitry still further comprises signal summing circuitry arranged to add the DC cancellation signal in anti-phase with the main path signal.
1. A receiver circuitry for processing a received Very Low Intermediate Frequency signal, said receiver circuitry comprising:
a main processing path comprising mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal; and
a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal; and
signal summing circuitry arranged to sum the DC cancellation signal in anti-phase with the main path signal.
2. The receiver circuitry of claim 1 , wherein the DC cancellation path further comprises narrow band filtering circuitry arranged to filter out non-DC elements of the received signal to obtain the DC element of the received signal.
3. The receiver circuitry of claim 2 , wherein the main processing path further comprises channel selectivity filtering.
4. The receiver circuitry of claim 2 , wherein the DC cancellation path further comprises Root Mean Square logic arranged to scale the amplitude of the DC cancellation signal.
5. The receiver circuitry of claim 2 , wherein the received signal comprises In-phase and Quadrature components.
6. The receiver circuitry of claim 2 , wherein the receiver circuitry further comprises analogue to digital converter circuitry for converting the received signal from an analogue from to a digital form prior to mixing the received VLIF signal with the conversion signal to produce a main path signal.
7. The receiver circuitry of claim 1 , wherein the DC cancellation path further comprises DC averaging circuitry arranged to filter out non-DC elements of the received signal to obtain the DC element of the received signal.
8. The receiver circuitry of claim 7 , wherein the main processing path further comprises channel selectivity filtering.
9. The receiver circuitry of claim 7 , wherein the DC cancellation path further comprises Root Mean Square logic arranged to scale the amplitude of the DC cancellation signal.
10. The receiver circuitry of claim 7 , wherein the received signal comprises In-phase and Quadrature components.
11. The receiver circuitry of claim 1 , wherein the main processing path further comprises channel selectivity filtering.
12. The receiver circuitry of claim 11 , wherein the DC cancellation path further comprises Root Mean Square logic arranged to scale the amplitude of the DC cancellation signal.
13. The receiver circuitry of claim 1 , wherein the DC cancellation path further comprises Root Mean Square logic arranged to scale the amplitude of the DC cancellation signal.
14. The receiver circuitry of claim 1 , wherein the received signal comprises In-phase and Quadrature components.
15. The receiver circuitry of claim 14 , wherein the DC cancellation path further comprises phase adjustment logic, arranged to adjust the phase of an oscillator signal in proportion to the magnitude of the I and Q DC terms.
16. The receiver circuitry of claim 1 , wherein the receiver circuitry further comprises analogue to digital converter circuitry for converting the received signal from an analogue from to a digital form prior to mixing the received VLIF signal with the conversion signal to produce a main path signal.
17. The receiver circuitry of claim 1 , wherein the mixing circuitry is arranged to mix the received signal with a frequency down conversion signal to produce a main path signal such that elements of the received signal are shifted to be centered at zero hertz.
18. An integrated circuit including receiver circuitry as claimed in claim 1 .
19. A wireless communication unit comprising:
receiver circuitry for processing a received Very Low Intermediate Frequency signal, said receiver circuitry comprising:
a main processing path comprising mixing circuitry arranged to mix a received VLIF signal with a frequency down conversion signal to produce a main path signal; and
a direct current cancellation path comprising mixing circuitry arranged to mix a DC element of the received VLIF signal with the frequency down conversion signal to produce a DC cancellation signal; and
signal summing circuitry arranged to sum the DC cancellation signal in anti-phase with the main path signal.
20. A method for processing a received Very Low Intermediate Frequency signal comprising:
mixing a received VLIF signal with a conversion signal to produce a main path signal;
obtaining a DC element of the received VLIF signal;
mixing the DC element of the received signal with the conversion signal to produce a DC cancellation signal; and
adding the DC cancellation signal in anti-phase with the main path signal.