Memory mapping system, request controller, multi-processing arrangement, central interrupt request controller, apparatus, method for controlling memory access and computer program product
View Patent ↗A memory mapping system is connectable to a multi-processing arrangement. The multi-processing arrangement includes a first processing unit and a second processing unit. The memory mapping system includes a main memory to which the second processing unit does not have write access, the main memory including a first memory section and a second memory section. An associated memory is associated with the second memory section. The associated memory includes a memory section to which the second processing unit has write access. A consistency control unit can maintaining consistency between data stored in the associated memory and data stored in the second memory section.
1. A memory mapping system comprising a multi-processing arrangement, said multi-processing arrangement including a first processing unit and a second processing unit, said memory mapping system comprising:
a main memory to which said second processing unit does not have write access, said main memory including a first memory section and a second memory section;
an associated memory associated with said second memory section, said associated memory including a memory section to which said second processing unit has write access;
a consistency control unit for maintaining consistency between data stored in said associated and data stored in said second memory section:
wherein data to be used by said second processing unit can be stored in said parts of the second memory section to which said first processing unit has write access and data to be used by said first processing unit can be stored in said parts of the associated memory to which said second processing unit has write access.
2. A memory mapping system as claimed in claim 1 , wherein said first processing unit has write access to at least said first memory section of said main memory.
3. A memory mapping system as claimed in claim 2 , wherein said associated memory has a blocked memory section to which said second processing unit does not have write access and said first processing unit has write access to parts of said second memory section associated with said blocked memory section.
4. A memory mapping system as claimed in claim 1 , wherein said associated memory has a blocked memory section to which said second processing unit does not have write access and said first processing unit has write access to parts of said second memory section associated with said blocked memory section.
5. A memory mapping system as claimed in claim 4 , wherein said first memory section has a blocked memory section to which said first processing unit does not have write access and said second processing unit has write access to parts of said associated memory which are associated with said blocked memory section of the second memory section.
6. A memory mapping system as claimed in claim 4 , wherein the first processing unit has write access to store request demand messages in said part of said second memory section associated with said blocked memory section and the second processing unit has write access to store request handled messages in an un-blocked part of the associated memory.
7. A memory mapping system as claimed in claim 1 , wherein said second memory section and said associated memory both include a request handling memory in which data about a handling of requests is stored.
8. A memory mapping system as claimed in claim 1 , wherein said second memory section and said associated memory are spaced apart and a distance between said second memory section and said associated memory exceeding a granularity of a memory protection scheme.
9. A memory mapping system as claimed in claim 1 , wherein said first memory section contains configuration data and only said first processing unit has write access to said first memory section.
10. A memory mapping system as claimed in claim 1 , including at least two associated memories, to which a respective second processing unit has write access and to which the other processing units do not have write access.
11. A request controller for controlling a processing of requests by a first processing unit and a second processing unit, said request controller including a memory mapping system as claimed in claim 1 and being arranged to control one or more of: interrupt requests, context switch requests, task switch requests, thread switch requests, process switch requests, inter processor interrupt requests, software interrupt requests, hardware interrupt requests.
12. A request controller as claimed in claim 11 , said request controller being a central interrupt request controller.
13. A multi-processing arrangement, comprising:
a first processing unit;
a second processing unit; and
a request controller as claimed in claim 1 .
14. A multi-processing arrangement as claimed in claim 13 , including a plurality of processing units of which a main safety processing unit forms the first processing unit is and a redundant processing unit forms said second processing unit is and wherein a selection of said main safety processing unit is configurable.
15. A multi-processing arrangement as claimed in claim 13 , wherein said main safety processing unit is selected based upon a safety level of the processing unit.
16. A multi-processing arrangement as claimed in claim 13 , wherein said first processing unit and/or said second processing unit are arranged to execute a software application and wherein said memory mapping system is transparent for said software application.
17. A multi-processing arrangement as claimed in claim 13 , implemented as a single integrated circuit.
18. A method of controlling memory access by a first processing unit and a second processing unit, comprising:
inhibiting said second processing unit to write to a main memory to which said second processing unit does not have write access, said main memory including a first memory section and a second memory section;
allowing said second processing unit to write to an associated memory associated with said second memory section, said associated memory including a memory section to which said second processing unit has write access; and
maintaining consistency between data stored in said associated memory and said second memory section,
wherein data to be used by said second processing unit can be stored in said parts of the second memory section to which said first processing unit has write access and data to be used by said first processing unit can be stored in said parts of the associated memory to which said second processing unit has write access.
19. A memory mapping system comprising a multi-processing arrangement, said multi-processing arrangement including a first processing unit and a second processing unit, said memory mapping system comprising:
a main memory to which said second processing unit does not have write access, said main memory including a first memory section and a second memory section;
an associated memory associated with said second memory section, said associated memory including a memory section to which said second processing unit has write access; and
a consistency control unit for maintaining consistency between data stored in said associated memory and data stored in said second memory section,
wherein said second memory section and said associated memory both include a request handling memory in which data about a handling of requests is stored.