Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor
View Patent ↗A capacitor and an NVM cell are formed in an integrated fashion so that the etching of the capacitor is useful in end point detection of an etch of the NVM cell. This is achieved using two conductive layers over an NVM region and over a capacitor region. The first conductive layer is patterned in preparation for a subsequent patterning step which includes a step of patterning both the first conductive layer and the second conductive layer in both the NVM region and the capacitor region. The subsequent etch provides for an important alignment of a floating gate to the overlying control gate by having both conductive layers etched using the same mask. During this subsequent etch, the fact that first conductive material is being etched in the capacitor region helps end point detection of the etch of the first conductive layer in the NVM region.
1. A method of making a capacitor over a capacitor region of a substrate and a non-volatile memory cell in an NVM region of the substrate, comprising:
forming a first dielectric layer on the substrate in the capacitor region and the NVM region;
forming a first conductive layer on the first dielectric layer;
performing a patterned etch of the first conductive layer in the capacitor region to form a bottom capacitor layer having a first side and a second side in the capacitor region;
forming a second dielectric layer on the bottom capacitor layer;
forming a second conductive layer on the second dielectric layer and extending past the first side and the second side of the bottom capacitor layer;
performing a patterned etch of the second conductive layer that leaves a patterned second conductive layer having a first side and a second side, wherein a top portion of the bottom capacitor layer is exposed between the first side of the patterned second conductive layer and the first side of the bottom capacitor layer and the second side of the patterned conductive layer extends past the second side of the bottom capacitor layer;
forming a first mask over the capacitor region having a first pattern, wherein the first pattern is of a top capacitor electrode region and a second mask over the NVM region having a second pattern, wherein the second pattern includes a pattern of a control gate of an NVM bit cell; and
performing an etch through the patterned second conductive layer, the second dielectric layer, and the bottom capacitor layer to leave the top capacitor electrode region from the patterned second conductive layer that extends past the bottom capacitor layer on the second side of the bottom capacitor layer, wherein third sides of the bottom capacitor layer and the top capacitor electrode region are aligned, fourth sides opposite from the third sides of the bottom capacitor layer and the top capacitor electrode region are aligned, and to leave the control gate from the patterned second conductive layer over a floating gate.
2. The method of claim 1 , further comprising forming a first contact to the exposed portion of the first conductive layer.
3. The method of claim 2 , further comprising forming a second contact to the second conductive layer, wherein the first contact and the second contacts are contacts of the capacitor.
4. The method of claim 1 , wherein the control gate is a portion of a word line.
5. The method of claim 1 , wherein the first conductive layer comprises polysilicon and the second conductive layer comprises polysilicon.
6. The method of claim 5 , wherein the step of performing the patterned etch of the second conductive layer that leaves the patterned second conductive layer having the first side and the second side is performed such that the second dielectric layer is also patterned and etched with the second conductive layer.
7. The method of claim 1 , wherein the step of performing a patterned etch of the second conductive layer that leaves a patterned second conductive layer is performed such that the second dielectric layer is also patterned and etched with the second conductive layer to leave a patterned second dielectric layer.
8. The method of claim 1 , further comprising forming a well region in the substrate as the capacitor region, wherein the step of implanting is further characterized as forming a doped contact region in the well region adjacent to first conductive layer and second conductive layer to function as a contact to an electrode of a second capacitor present between the well region and the first conductive layer and a third capacitor present between the well region and the second conductive layer.
9. The method of claim 1 , further comprising forming an interlayer dielectric over the gate stack, the second conductive layer in the capacitor region, and the exposed portion of the first conductive layer in the capacitor region.
10. The method of claim 9 , further comprising forming a first contact through the interlayer dielectric to the second conductive layer that extends past the bottom capacitor layer.
11. The method of claim 1 , further comprising:
performing an implant using the control gate as a mask to provide source/drain regions in the NVM region.
12. A method of making a capacitor over a capacitor region of a substrate and a non-volatile memory cell in an NVM region of semiconductor substrate, comprising:
growing an oxide layer on the substrate in the capacitor region and the NVM region;
forming a polysilicon layer on the oxide layer;
performing a patterned etch of the polysilicon layer in the capacitor region and the NVM region to form a patterned polysilicon layer having a bottom electrode layer having a first side and a second side parallel to the first side in the capacitor region and a floating gate layer in the NVM region;
forming an insulating layer on the patterned polysilicon layer;
forming a conductive layer on the insulating layer and extending over the capacitor region and the NVM region;
performing a patterned etch of the conductive layer to leave a top electrode layer from the conductive layer over the capacitor region, wherein the top electrode layer has a first side over the bottom electrode layer and a second side spaced away from the bottom electrode layer, and wherein the first and second sides of the top electrode layer are parallel to the first and second sides of the bottom electrode layer;
forming a first mask over the capacitor region having a first pattern, wherein the first pattern is of a top capacitor electrode and a second mask over the NVM region having a second pattern, wherein the second pattern is of a control gate of an NVM bit cell;
performing an etch through the top electrode layer, the insulating layer, the bottom capacitor layer, the conductive layer over the NVM region, and the floating gate layer to leave the first pattern of the top electrode layer and a bottom electrode from the bottom capacitor layer and the control gate from the conductive layer over the NVM region and a floating gate from the floating gate layer, wherein the top electrode has formed a third side and a fourth side parallel to the third side between the first and second sides of the top electrode layer, the bottom electrode has formed a third side and a fourth side parallel to the third side between the first and second sides of the bottom electrode layer, the third side of the top electrode is aligned with the third side of the bottom electrode, the fourth side of the top electrode is aligned with the fourth side of the bottom electrode, the floating gate has a third side and a fourth side parallel to the third side between the first and second sides of the floating gate layer, and the control gate has a first side aligned with the third side of the floating gate and a second side aligned with the fourth side of the floating gate; and
performing an implant using the control gate as a mask to provide source/drain regions adjacent to the control gate in the NVM region.
13. The method of claim 12 , further comprising forming a first contact on the bottom electrode.
14. The method of claim 13 , further comprising forming a second contact on the top electrode.
15. The method of claim 12 , wherein the control gate comprises polysilicon.
16. The method of claim 12 , wherein the control gate further comprises silicide.
17. The method of claim 12 , further comprising forming a well region in the substrate as the capacitor region, wherein the step of implanting is further characterized as forming a doped contact region in the well region around the top electrode and bottom electrode.
18. The method of claim 12 , further comprising forming an interlayer dielectric over the gate, the conductive layer in the capacitor region, and the exposed portion of the polysilicon layer in the capacitor region.
19. The method of claim 18 , further comprising forming a first contact through the interlayer dielectric to the to a portion of the top electrode that extends past the bottom electrode.
20. A method of making a capacitor over a capacitor region of a substrate and a non-volatile memory cell in an NVM region of semiconductor substrate, comprising:
forming a well region in the capacitor region of the substrate;
growing an oxide layer on the substrate in the well region and the NVM region as a gate dielectric;
forming a first polysilicon layer on the oxide layer;
performing a patterned etch of the polysilicon layer in the well region and the NVM region to form a bottom electrode layer in the well region and a floating gate layer in the NVM region;
forming an insulating layer on the polysilicon layer;
forming a conductive layer on the insulating layer and over the well region and the NVM region;
performing a patterned etch of the conductive layer over the well region to form a patterned conductive layer, wherein the patterned conductive layer has a first side on the bottom electrode layer to expose a first portion of the bottom electrode layer and a second side parallel to the first side spaced away from the bottom electrode layer; and
performing a patterned etch through the conductive layer, the insulating layer, the bottom capacitor layer, and the floating gate layer to leave a bottom electrode from the bottom electrode layer, a top electrode from the top electrode layer, a control gate from the conductive layer over the NVM region, and a floating gate from the floating gate layer, wherein the bottom electrode has a covered portion covered by the top electrode and an uncovered portion not covered by the top electrode, the top electrode has a extended portion spaced from the bottom electrode, and the control gate extends past the floating gate in a first direction and has a first side aligned to a first side of the floating gate and a second side aligned to a second side of the floating gate.