Granted Patent B2

US 8,543,766 · App. 13/157,549 · Granted Sep 24, 2013

Abstract

Claims (82)

1. A method comprising:

storing a state indicator associated with a cache line wherein the state indicator is stored in a tracking entry associated with a region of system memory, wherein

the cache line is one of a plurality of cache lines each associated with a corresponding unique section of the region of system memory, wherein the plurality of cache lines includes N cache lines in which N is a number of cache lines needed to store all of the region of system memory,

the state indicator is one of a plurality of state indicators each associated with a corresponding cache line of the plurality of cache lines such that every cache line of the plurality of cache lines has an associated state indicator of the plurality of state indicators; and

the tracking entry comprises each of the plurality of state indicators, wherein each state indicator comprises:

a dirty indication when the associated cache line is a candidate for writing data stored in the cache line to the associated section of the region of system memory, and

a clean indication when the associated cache line is not a candidate for writing data stored in the cache line to the associated section of the region of system memory,

determining, for the region of system memory, a number of the plurality of state indicators that comprise the dirty indication; and

if the determined number of dirty indications exceeds a threshold, then selecting a cache line,

writing the data stored in the cache line to the associated section of the region of system memory, and

storing a clean indication in the state indicator corresponding to the cache line, wherein the clean indication identifies that the cache line is not a candidate for writing data stored in the cache line to the associated section of the region of system memory.

2. The method of claim 1 further comprising:

performing said selecting the cache line, said writing the data stored in the cache line, and said storing a clean indication for a selected number of cache lines associated with the region of system memory, each of the selected number of cache lines having an associated state indicator comprising the dirty indication, if the determined number of dirty indications exceeds the threshold.

3. The method of claim 1 further comprising:

storing the tracking entry in a tracking array, wherein

the tracking array comprises a plurality of tracking entries, and

each of the plurality of tracking entries is associated with a unique region of system memory.

4. The method of claim 3 further comprising:

performing said determining and said selecting using a cache cleaning control circuitry coupled to a memory storing the tracking array.

5. The method of claim 3 further comprising:

storing the number of state indicators that comprise the dirty indication in a counter associated with the tracking entry, wherein

said storing is performed for each of the plurality of tracking entries.

6. The method of claim 3 further comprising:

receiving a memory access message comprising an access address and one or more attributes associated with the memory access;

if no tracking entry matches a region of system memory referred to in the access address, then allocating a new entry in the tracking array, wherein the new entry corresponds to the region of system memory referred to in the access address, if the one or more attributes provide that the memory access message causes a cache line to become a candidate for writing data stored in the cache line to the associated section of the region of system memory; and

performing said storing the state indicator associated with the cache line, if the one or more attributes provide that the memory access message causes the cache line to become a candidate for writing data stored in the cache line to the associated section of the region of system memory, wherein

the state indicator is stored in one of the new entry in the tracking array or a tracking entry that matches the region of system memory referred to in the access address.

7. The method of claim 6 further comprising:

storing a clean indication in the state indicator corresponding to the cache line, if the one or more attributes provide that the memory access message indicates an intent to make the cache line become a candidate for writing data stored in the cache line as a result of a subsequent access.

8. The method of claim 7 further comprising

incrementing the number of the plurality of state indicators that comprise the dirty indication for the associated tracking entry, if the one or more attributes provide that the memory access message causes the cache line to become a candidate for writing data stored in the cache line to the associated section of the region of system memory; and

decrementing the number of the plurality of state indicators that comprise the dirty indication for the associated tracking entry, if the one or more attributes provide that the memory access message indicates an intent to make the cache line become a candidate for writing data stored in the cache line as a result of a subsequent access.

9. The method of claim 1 wherein one or more of a system cache memory and processor cache memories, each corresponding to a processor, comprise the plurality of cache lines.

10. A system comprising:

one or more masters, each master comprising one of a processor or a peripheral device;

a system memory comprising a plurality of system memory banks, wherein

each system memory bank comprises a plurality of unique rows, and

each row corresponds to a region of the system memory;

one or more cache memories, coupled to the one or more masters, and storing a plurality of cache lines, wherein

each cache line is associated with a corresponding unique section of a row of the plurality of rows,

each cache line is configured to store data associated with the corresponding unique section of a row for access by the one or more processors, and

the one or more cache memories comprise one or more of a system cache and a dedicated cache associated with a corresponding processor; and

a cache cleaning circuitry, coupled to the one or more cache memories, and configured to

store a plurality of state indicators each associated with a corresponding cache line of the plurality of cache lines, wherein each state indicator comprises one of a dirty indication that the corresponding cache line is a candidate for writing data stored in the cache line to the corresponding unique section of the row or a clean indication that the corresponding cache line is not a candidate for writing data stored in the cache line,

select a row having a number of state indicators comprising the dirty indication exceeding a threshold, and

for the selected row, select one or more cache lines each having a corresponding state indicator comprising the dirty indication, write the data stored in the selected cache lines to the corresponding sections of the row, and store a clean indication in the state indicator,

wherein the state indicator is stored in a tracking entry associated with the row, wherein the tracking entry comprises N state indicators of the plurality of state indicators associated with the cache lines associated with the row, in which N represents a number of cache lines needed to store all of the row.

11. The system of claim 10 wherein the cache cleaning circuitry further comprises:

a tracking array memory storing a tracking array, wherein

the tracking array comprises a plurality of tracking entries, and

each of the plurality of tracking entries is associated with a unique row.

12. The system of claim 11 wherein the cache cleaning circuitry is further configured to:

store a number of dirty indications for a tracking entry in a counter associated with the tracking entry.

13. The system of claim 11 wherein the cache cleaning circuitry is further configured to:

receive a memory access message from a master of the one or more masters, wherein the memory access message comprises an access address and one or more attributes associated with the memory access;

determine if a tracking entry matches a row referred to in the access address;

allocate a new entry in the tracking array corresponding to the row referred to in the access address,

if no tracking entry matches the row referred to in the access address, and

if the one or more attributes provide that the memory access message causes a cache line to become a candidate for writing data stored in the cache line to the associated section of the row;

perform said storing the state indicator associated with the cache line, if the one or more attributes provide that the memory access message causes the cache line to become a candidate for writing data stored in the cache line to the associated section of the row, wherein

the state indicator is stored in one of the new entry in the tracking array or a tracking entry that matches the row referred to in the access address; and

increment the number of state indicators comprising the dirty indication for the associated tracking entry, if the one or more attributes provide that the memory access message causes the cache line to become a candidate for writing data stored in the cache line to the associated section of the row.

14. The system of claim 13 wherein the cache cleaning circuitry is further configured to:

store a clean indication in the state indicator associated with the cache line, if the one or more attributes provide that the memory access message indicates an intent to make the cache line become a candidate for writing data stored in the cache line as a result of a subsequent access; and

decrement the number of state indicators comprising the dirty indication for the associated tracking entry, if the one or more attributes provide that the memory access message indicates an intent to make the cache line become a candidate for writing data stored in the cache line as a result of a subsequent access.

15. The system of claim 10 wherein the tracking entry comprises a bit field wherein one or more bits in the bit field stores one of the N state indicators.

16. The system of claim 10 , wherein

each of the plurality of state indicators comprises an identifier of a cache memory storing the associated cache line and the write indication for the associated cache line.

17. The system of claim 10 , wherein the cache cleaning circuitry is further configured to:

store a number of dirty indications for a tracking entry in a counter associated with the tracking entry.

18. A method comprising:

determining whether one or more tracking entries comprise a number of dirty indications that exceeds a predetermined threshold, wherein

each tracking entry comprises a plurality of cache line fields each having a corresponding cache line associated with a unique section of the same region of system memory, wherein the plurality of cache line fields includes N cache line fields in which N represents a number of cache lines needed to store all of the same region of system memory, and wherein each cache line field comprises:

a dirty indication when the corresponding cache line is a candidate for writing data stored in the cache line to the associated unique section; and

a clean indication when the corresponding cache line is not a candidate for writing data stored in the cache line to the associated unique section;

selecting a tracking entry of the one or more tracking entries having a number of dirty indications exceeding the predetermined threshold;

selecting a dirty cache line associated with the selected tracking entry;

transmitting a transaction to a cache storing the selected cache line, wherein the transaction is configured to cause the cache to write the dirty data to a system memory;

storing a clean indication in the state indicator corresponding to the selected tracking entry to indicate that the cache line is no longer a candidate for writing data to system memory;

performing said selecting the cache line, transmitting, and storing for a predetermined number of cache lines;.

storing a count of dirty indications for each tracking entry, wherein the dirty indications correspond to cache lines storing dirty data; and

storing a new count of dirty indications for the associated tracking entry subsequent to said transmitting the transaction.

Assignments (17)