In-line register file bitcell
View Patent ↗An SRAM bitcell architecture is described having a dedicated read port (N 0 /N 1 /N 6 , N 3 /N 4 /N 7 ) with pull up transistors (N 6 , N 7 ) that shares at least a first bit line pair ( 23, 24 ) and word line signal ( 25 ), thereby providing separate data access read paths to a 6T SRAM architecture such that the read port is connected to drive the cell read node without exposing the memory cell during read operations and to act as a write port during write operations.
1. A memory comprising:
a plurality of memory cells arranged in rows and columns;
a plurality of word lines running in a row direction;
a plurality of bit line pairs running in a column direction for reading and writing memory cell data; and
a plurality of write enable lines running in a column direction;
where the plurality of memory cells comprises a plurality of static random access memory (SRAM) cells, each comprising:
a memory unit comprising two cross-coupled inverters for storing data at first and second internal nodes;
two data access devices respectively coupled to the first and second internal nodes and controlling the cross-coupled inverters to enable data to be written from a pair of external nodes under control of a write enable line supplied to the SRAM cell; and
two read port devices respectively connected between the first and second internal nodes and a bit line pair supplied to the SRAM cell to enable data to be read from the memory unit under control of a word line supplied to the SRAM cell when the data access devices are turned off, where each read port device comprises a pull up device coupled to an external node, where each read port device comprises:
a first transistor which is source-drain coupled between one of the pair of external nodes and one bit line of the bit line pair supplied to the SRAM cell and which is gated by the word line supplied to the SRAM cell;
a second transistor which is source-drain coupled between one of the pair of external nodes and a first ground reference voltage and which is gated by one of the first and second internal nodes;
a third transistor which is source-drain coupled between one of the pair of external nodes and a pull up node and which is gated by the other of the first and second internal nodes; and
a fourth transistor which is source-drain coupled between the pull up node and a second supply reference voltage and which is gated by the write enable line supplied to the SRAM cell.
2. The memory of claim 1 , where each of the cross-coupled inverters is formed with an NMOS and PMOS transistor pair.
3. The memory of claim 1 , where each of the data access devices comprises an access transistor which is source-drain coupled between the memory unit and one of the pair of external nodes and which is gated by the write enable line supplied to the SRAM cell.
4. The memory of claim 1 , where each of the cross-coupled inverters is formed with an NMOS and PMOS transistor pair that is coupled to the second supply reference voltage by a PMOS transistor which is gated by the write enable line supplied to the SRAM cell, thereby turning off the inverter during a write operation.
5. The memory of claim 1 , where the memory unit further comprises a pair of bit line access devices respectively connected between the pair of external nodes and a second bit line pair supplied to the SRAM cell and gated by the word line supplied to the SRAM cell to enable data to be read from the memory unit under control of the word line when the data access devices are turned off.
6. The memory of claim 1 , where the each static random access memory cell is interleaved with a plurality of six-transistor SRAM cells.
7. A static random access memory (SRAM) cell, comprising:
a memory unit comprising two cross-coupled inverters for storing data at a pair of storage nodes via switching activities of the inverters, where each of the inverters is formed with an NMOS and PMOS transistor pair that is coupled to a supply reference voltage by a PMOS transistor which is gated by a write enable line supplied to the SRAM cell, thereby turning off the inverters during a write operation;
two data access transistors respectively connected between a pair of cell read nodes and the pair of storage nodes for writing data to the memory unit under control of a write enable line;
two read port devices, each connected between a bit line and a storage node in the memory unit to provide a data access path under control of a word line to drive a cell read node without exposing the storage node of the memory cell during read operations; and
a pull up transistor device connected to each read port device.
8. The SRAM cell of claim 7 , where each of the two data access transistors comprises an NMOS transistor which is source-drain coupled between the memory unit and one of the pair of cell read nodes and which is gated by the write enable line.
9. The SRAM cell of claim 7 , where each of the two read port devices comprises:
a first transistor which is source-drain coupled between one of the pair of cell read nodes and one bit line of a bit line pair supplied to the SRAM cell and which is gated by the word line supplied to the SRAM cell; and
a second transistor which is source-drain coupled between one of the pair of cell read nodes and a ground reference voltage and which is gated by a first storage node from the pair of storage nodes.
10. The SRAM cell of claim 9 , where the pull up transistor device comprises a third transistor which is source-drain coupled between one of the pair of cell read nodes and a supply reference voltage and which is gated by a second storage node from the pair of storage nodes.
11. The SRAM cell of claim 10 , where the pull up transistor device further comprises a fourth transistor which is source-drain coupled between the third transistor and the supply reference voltage and which is gated by the write enable line supplied to the SRAM cell.
12. The SRAM cell of claim 7 , further comprising an additional pair of bit line access transistors respectively connected between the pair of cell read node and the bit line pair supplied to the SRAM cell and gated by the word line supplied to the SRAM cell to enable data to be read from the memory unit under control of the word line when the two data access transistors are turned off.
13. A static random access memory (SRAM) array comprising:
a plurality of memory cells arranged in rows and columns;
a plurality of word lines running in a row direction;
a plurality of bit line pairs running in a column direction; and
a plurality of write enable lines running in a column direction;
where the plurality of memory cells comprises:
a plurality of six-transistor (6T) SRAM cells arranged in rows and columns such that 6T SRAM cells in a column share a bit line pair and a write enable line and 6T SRAM cells in a row share a word line; and
a plurality of SRAM bitcells interleaved in the rows and columns such that bitcells in a column share a bit line pair and a write enable line and bitcells in a row share a word line, where each bitcell comprises a write port and a read port sharing a common bit line pair and a common word line such that the read port does not disturb the bitcell when connected to the bit line pair by the common word line.
14. The SRAM array of claim 13 , where each of the plurality of SRAM bitcells comprises a static random access memory (SRAM) cell comprising:
a memory unit comprising two cross-coupled inverters for storing data at a pair of storage nodes via switching activities of the inverters;
two data access transistors respectively connected between a pair of cell read nodes and the pair of storage nodes in the memory unit for controlling said two inverters to enable data to be written from the common bit line pair to the pair of storage nodes under control of a write enable line;
two read ports connected to the common bit line pair and a word line, and providing additional data access paths to drive the pair of cell read nodes without exposing the pair of storage nodes of the memory cell during read operations and to act as a write port during write operations; and
a pull up device connected to each cell read node.
15. The SRAM array of claim 14 , where each of the two read ports comprises:
a first transistor which is source-drain coupled between one of the pair of cell read nodes and one bit line of a bit line pair supplied to the SRAM cell and which is gated by the word line supplied to the SRAM cell; and
a second transistor which is source-drain coupled between one of the pair of cell read nodes and a ground reference voltage and which is gated by one of the pair of storage nodes.
16. The SRAM array of claim 15 , where the pull up device comprises a third transistor which is directly or indirectly source-drain coupled between one of the pair of cell read nodes and a supply reference voltage and which is gated by the other of the pair of storage nodes.
17. A memory comprising:
a plurality of memory cells arranged in rows and columns;
a plurality of word lines running in a row direction;
a plurality of bit line pairs running in a column direction for reading and writing memory cell data; and
a plurality of write enable lines running in a column direction;
where the plurality of memory cells comprises a static random access memory (SRAM) cell comprising:
a memory unit comprising two cross-coupled inverters for storing data at first and second internal nodes;
two data access devices respectively coupled to the first and second internal nodes and controlling the cross-coupled inverters to enable data to be written from a pair of external nodes under control of a write enable line supplied to the SRAM cell; and
two port devices respectively connected between the first and second internal nodes and a first bit line pair supplied to the SRAM cell to enable data to be read from the memory unit under control of a word line supplied to the SRAM cell when the data access devices are turned off, where each port device comprises:
a first pair of bitline access devices respectively connected between the pair of external nodes and a first bitline pair supplied to the SRAM cell and gated by the word line supplied to the SRAM cell to enable data to be read from the memory unit under control of the word line when the data access devices are turned off; and
a second pair of bitline access devices respectively connected between the pair of external nodes and a second bitline pair supplied to the SRAM cell and gated by the word line supplied to the SRAM cell to enable data to be read from the memory unit under control of the word line when the data access devices are turned off.
18. A memory comprising:
a plurality of memory cells arranged in rows and columns;
a plurality of word lines running in a row direction;
a plurality of bit line pairs running in a column direction for reading and writing memory cell data; and
a plurality of write enable lines running in a column direction;
where the plurality of memory cells comprises a plurality of static random access memory (SRAM) cells, each comprising:
a memory unit comprising two cross-coupled inverters for storing data at first and second internal nodes;
two data access devices respectively coupled to the first and second internal nodes and controlling the cross-coupled inverters to enable data to be written from a pair of external nodes under control of a write enable line supplied to the SRAM cell; and
two read port devices respectively connected between the first and second internal nodes and a bit line pair supplied to the SRAM cell to enable data to be read from the memory unit under control of a word line supplied to the SRAM cell when the data access devices are turned off, where each read port device comprises a pull up device coupled to an external node, where each read port device comprises:
a first transistor which is source-drain coupled between one of the pair of external nodes and one bit line of the bit line pair supplied to the SRAM cell and which is gated by the word line supplied to the SRAM cell;
a second transistor which is source-drain coupled between one of the pair of external nodes and a first ground reference voltage and which is gated by one of the first and second internal nodes; and
a third transistor which is source-drain coupled between one of the pair of external nodes and a second supply reference voltage and which is gated by the other of the first and second internal nodes, thereby forming the pull up device,
where each of the cross-coupled inverters is formed with an NMOS and PMOS transistor pair that is coupled to the second supply reference voltage by a PMOS transistor which is gated by the write enable line supplied to the SRAM cell, thereby turning off the inverter during a write operation.
19. A static random access memory (SRAM) cell, comprising:
a memory unit comprising two cross-coupled inverters for storing data at a pair of storage nodes via switching activities of the inverters;
two data access transistors respectively connected between a pair of cell read nodes and the pair of storage nodes for writing data to the memory unit under control of a write enable line;
two read port devices, each connected between a bit line and a storage node in the memory unit to provide a data access path under control of a word line to drive a cell read node without exposing the storage node of the memory cell during read operations, where each of the two read port devices comprises:
a first transistor which is source-drain coupled between one of the pair of cell read nodes and one bit line of a bit line pair supplied to the SRAM cell and which is gated by the word line supplied to the SRAM cell, and
a second transistor which is source-drain coupled between one of the pair of cell read nodes and a ground reference voltage and which is gated by a first storage node from the pair of storage nodes; and
a pull up transistor device connected to each read port device, where the pull up transistor device comprises:
a third transistor which is source-drain coupled between one of the pair of cell read nodes and a supply reference voltage and which is gated by a second storage node from the pair of storage nodes, and
a fourth transistor which is source-drain coupled between the third transistor and the supply reference voltage and which is gated by the write enable line supplied to the SRAM cell.