Selective error detection and error correction for a memory interface
View Patent ↗Error correction code (ECC) checkbits are generated for each write access to a memory address based on both the data to be written (the write data) and the memory address. The ECC checkbits are stored with the write data at the memory device associated with the memory address. In addition, the memory device can selectively perform error detection and correction for write accesses using the ECC checkbits. For example, the memory device can include an ECC control register that stores control information to selectively enable and disable error detection and correction for write accesses. In an embodiment, error detection and correction can be selectively enabled and disabled for different sizes of write data.
1. In a data processing device comprising a processor unit coupled to a memory, a method comprising:
receiving a write access comprising data to be written to the memory; and
executing a first error detection procedure in response to receiving the write access, the first error detection procedure comprising:
in response to determining the data is of a first size, performing error detection on the data; and
in response to determining the data is of a second size, writing the data to memory without performing error detection on the data.
2. The method of claim 1 , wherein executing the first error detection procedure comprises performing the first error detection procedure in response to determining access control policy information indicates a first access policy, and further comprising:
in response to determining the access control policy information indicates a second access policy, writing the data to memory without performing error detection when the data is of the first size and when the data is of the second size.
3. The method of claim 1 , wherein executing the first error detection procedure comprises executing the first error detection procedure in response to determining access control policy information indicates a first access policy, and further comprising:
in response to determining the access control policy information indicates a second access policy, performing error detection prior to writing the data to memory when the data is of the first size and when the data is of the second size.
4. The method of claim 3 , further comprising:
in response to determining the access control policy information indicates the second access policy, performing error correction on the data in response to detecting an error; and
in response to determining the access control policy information indicates a third access policy:
performing error detection when the data is of the first size and when the data is of the second size; and
indicating an error to the processor unit in response to detecting an error without performing error correction on the data.
5. The method of claim 1 , wherein performing error detection comprises performing error detection based on a set of ECC checkbits, the ECC checkbits based on a memory address associated with the memory request.
6. The method of claim 1 , wherein executing the first error correction procedure comprises executing the first error correction procedure at the memory, and further comprising:
performing a second error correction procedure at a module that generates the write access, the second error correction procedure generating a set of error correction code (ECC) checkbits for use by the first error correction procedure.
7. The method of claim 6 , further comprising:
receiving at the memory a read access for the data, the read access generated by a requesting module;
providing the data and ECC checkbits to the requesting module in response to the read access; and
performing error detection on the data at the requesting module based on the ECC checkbits.
8. The method of claim 1 , wherein the first size corresponds to a width of the memory.
9. A method, comprising:
receiving a write access comprising data to be written to the memory;
determining an access control policy in response to the write access; and
selectively performing a first error detection procedure on the data to be written to the memory based on the access control policy.
10. The method of claim 9 , further comprising:
providing the data from the memory to a requesting module via the interconnect in response to a read access; and
performing a second error detection procedure on the data at the requesting module in response to the memory providing the data
11. The method of claim 9 , wherein selectively performing the first error detection procedure comprises:
in response to determining the access control policy is a first policy, storing the data without performing error detection; and
in response to determining the access control policy is a second policy, performing error detection on the data.
12. The method of claim 9 , wherein selectively performing the first error detection procedure further comprises:
in response to determining the access control policy is the second policy, indicating an error to the source module in response to detecting an error.
13. The method of claim 12 , wherein selectively performing the first error detection procedure further comprises:
in response to determining the access control policy is the second policy, performing error correction on the data in response to detecting an error in the data; and
in response to determining the access control policy is a third policy:
performing error detection on the data prior to storing the data; and
storing the data without performing error correction in response to detecting an error in the data.
14. The method of claim 13 , wherein determining the access policy comprises determining the access policy based on a value stored at a register.
15. The method of claim 9 , wherein selectively performing the first error detection procedure further comprises:
selectively performing the first error detection procedure based on a size of the data.
16. The method of claim 15 , wherein selectively performing the first error detection procedure based on the size of the data comprises:
storing the data without performing error detection in response to determining the size of the data corresponds to a width of the memory; and
performing error detection prior to storing the data in response to determining the size of the data does not correspond to the width of the memory.
17. A data processing device, comprising:
a source module to generate, for a write access, a set of ECC checkbits based on data to be written;
a memory;
an interconnect to provide the write access to the memory;
a storage location to store access control policy information; and
the memory comprising an ECC module to selectively perform a first error detection procedure on the data based on the access control policy, the ECC module further to:
in response to determining the access control policy is a first policy:
perform error detection on the data prior to the memory storing the data; and
perform error correction on the data in response to detecting an error in the data; and
in response to determining the access control policy is a second policy:
perform error detection on the data prior to storing the data at the memory; and
store the data at the memory without performing error correction in response to detecting an error in the data.
18. The data processing device of claim 17 , further comprising:
a requesting module to generate a read request for the data, the memory to provide the data to the requesting module in response to the read request, the requesting module to perform a second error detection procedure on the data in response to the memory providing the data.
19. The data processing device of claim 17 , wherein the ECC module is to:
in response to determining the access control policy is a third policy, store the data at the memory without performing error detection.