LEAD FRAME FOR SEMICONDUCTOR DEVICE
A lead frame including a lead frame structure having a die support area and a plurality of electrical contact areas has shallow recesses formed on a surface of the lead frame structure.
1 . A lead frame, comprising:
a lead frame structure having a die support area and a plurality of electrical contact areas, wherein a shallow recess is formed on a surface of the lead frame structure.
2 . The lead frame of claim 1 , wherein the shallow recess is formed at least partially around a critical portion of the lead frame structure.
3 . The lead frame of claim 2 , wherein the critical portion comprises at least one of a die bonding area, a wire bonding area, and a moisture sensitive area.
4 . The lead frame of claim 2 , wherein the shallow recess is formed as a step at an edge of the critical portion.
5 . The lead frame of claim 1 , wherein the shallow recess is formed to a depth of between about 15 percent (%) and about 30% of a thickness of the lead frame structure.
6 . The lead frame of claim 5 , wherein the shallow recess is formed to a depth of between about 20% and about 25% of the thickness of the lead frame structure.
7 . The lead frame of claim 1 , wherein the shallow recess is formed over and on an opposite surface to an etched portion of the lead frame structure.
8 . The lead frame of claim 1 , wherein the shallow recess has a width of between about 0.1 millimeter (mm) and about 0.25 mm.
9 . A lead frame, comprising:
a lead frame structure having a die support area and a plurality of electrical contact areas, wherein a plurality of shallow recesses is formed on a surface of the lead frame structure at least partially around respective ones of a plurality of critical portions of the lead frame structure.
10 . The lead frame of claim 9 , wherein the critical portions comprise one or more of a die bonding area, a wire bonding area, and a moisture sensitive area.
11 . The lead frame of claim 9 , wherein the shallow recesses are formed to a depth of between about 15% and about 30% of a thickness of the lead frame structure.
12 . The lead frame of claim 11 , wherein the shallow recesses are formed to a depth of between about 20% and about 25% of the thickness of the lead frame structure.
13 . A semiconductor package, comprising:
a lead frame structure having a die support area and a plurality of electrical contact areas, wherein a shallow recess is formed on a surface of the lead frame structure;
an integrated circuit (IC) die attached to the die support area and electrically connected to the electrical contact areas; and
a molding compound encapsulating the IC die and a portion of the lead frame structure.
14 . The semiconductor package of claim 13 , wherein the shallow recess is formed at least partially around a critical portion of the lead frame structure.
15 . The semiconductor package of claim 14 , wherein the critical portion comprises one of a die bonding area, a wire bonding area, and a moisture sensitive area.
16 . The semiconductor package of claim 14 , wherein the shallow recess is formed as a step at an edge of the critical portion.
17 . The semiconductor package of claim 13 , wherein the shallow recess is formed to a depth of between about 15% and about 30% of a thickness of the lead frame structure.
18 . The semiconductor package of claim 17 , wherein the shallow recess is formed to a depth of between about 20% and about 25% of the thickness of the lead frame structure.
19 . The semiconductor package of claim 13 , wherein the shallow recess is formed over and on an opposite surface to a half-etched portion of the lead frame structure.
20 . The semiconductor package of claim 13 , wherein the shallow recess has a width of between about 0.1 millimeter (mm) and about 0.25 mm.