Method and apparatus for handling an output mismatch
View Patent ↗A system comprises a first signal processing logic module and at least one further signal processing logic module. The system further comprises mismatch handler logic module arranged to detect a mismatch between outputs of the first and at least one further signal processing logic module, the mismatch between outputs indicating a failed operation. The mismatch handler logic module further arranged, upon detection of a mismatch between outputs of the first and at least one further signal processing logic module, to analyze internal states of the first and at least one further signal processing logic module, determine whether the cause of the output mismatch is due to a transient fault, and upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronize the first and at least one further signal processing logic module.
1. A system comprising:
a first signal processor and a second signal processor, each of the first and second signal processor comprises a plurality of flip-flop elements arranged to form a scan chain when the respective signal processor is configured to operate in a mismatch handling mode; and
a mismatch handler logic module, the mismatch handler logic module to detect a mismatch between outputs of the first and second signal processor, the mismatch between outputs indicating a failed operation, the mismatch handler logic further comprising:
a first state analyzer logic module operably coupled to the first signal processor, and a second state analyzer logic module operably coupled to the second signal processor, wherein in response to detection of the mismatch the first and second state analyzer logic module are to analyze an internal state of the first and second processors respectively and are to generate a state signature value for the first and second signal processor respectively based at least on states of the respective plurality of flip-flop elements and to,
upon determination that the cause of the output mismatch is due to a transient fault, to re-synchronize the first and second signal processors.
2. The system of claim 1 wherein each of the first and second state analyzer logic module is arranged to receive state pre-processing configuration information, the state pre-processing configuration information substantially defining how the state analyzer logic generates the state signature value.
3. The system of claim 1 wherein the mismatch handler logic module is arranged, upon a comparison of state signature values of the first signal processor and the second signal processor determining matching internal states for the first and second signal processors, to cause the first and second signal processors to re-execute the failed operation.
4. The system of claim 3 wherein, upon re-execution of the failed operation, if the mismatch handler logic module detects a further mismatch between outputs of the first and second signal processor, the mismatch handler is further arranged to determine that the output mismatch is not due to a transient fault.
5. The system of claim 1 , wherein the first and second state analyzer logic module are arranged, upon a comparison of state signature values of the first and second signal processor determining mismatching internal states for the first and second signal processors, to determine whether the mismatch within the first and second signal processor, and thereby the output mismatch, is caused by a transient fault.
6. The system of claim 5 wherein, upon a comparison of internal states of the first and second signal processor determining mismatching internal states for the first and second signal processor, at least one of the first and second state analyzer logic module is arranged to re-load its respective signal processor with state values in order to re-synchronize the signal processor.
7. The system of claim 1 wherein the mismatch handler logic module further comprises sequence copy logic module, operably coupled to an input of a scan chain for each of the first and second signal processor, and arranged to introduce a sequence of state values into the input of the scan chains to re-synchronize the signal processor.
8. The system of claim 7 wherein the sequence copy logic module is further operably coupled an output of at least one of the scan chains for the signal processor, and arranged to introduce a sequence of state values from the output of the at least one scan chain into the of the scan chains to re-synchronize the signal processor.
9. The system of claim 1 wherein, upon determination that the output mismatch was not caused by a transient fault, the mismatch handler logic module is further arranged to cause the system to transition into a safe state.
10. A semiconductor device comprising the system of claim 1 .
11. A system comprising:
a first signal processor and a second signal processor; and
a first state analyzer logic module operably coupled to the first signal processor and a second state analyzer logic module operably coupled to the second signal processor, wherein upon detecting mismatching internal states for the first and second signal processors, each of the first and second state analyzer logic module are arranged to:
compare information relating to the internal state of the respective signal processor with information relating to internal states from previously detected internal mismatches; and
if a comparable mismatch has not previously been detected, to determine the that the mismatch within the first and second signal processor, and thereby the output mismatch, is caused by a transient fault.
12. The system of claim 11 wherein, upon a comparison of internal states of the first and second signal processor determining mismatching internal states for the first and second signal processor, each of the first and second state analyzer logic module is arranged to identify a location of fault causing the mismatch within the first and second signal processor.
13. A method comprising:
detecting a mismatch between outputs of a first signal processor and a second signal processor that is an indication of a failed operation;
in response to detecting the mismatch, comparing an internal state of the first signal processor and an internal state of the second signal processor to determine mismatching internal states;
in response to determining the mismatching internal states,
comparing information relating to the internal state of the respective first and second signal processor with information relating to internal states of the first and second signal processor from previously detected internal mismatches to determine if a comparable mismatch between internal states has been previously detected; and
in response to determining a comparable mismatch between internal states has not previously been detected, determining that the mismatching internal state between the first and second signal processors, and thereby the mismatch between outputs, is caused by a transient fault.
14. The method of claim 13 , wherein comparing the internal state of the first signal processor and the internal state of the second signal processor includes receiving the internal state of the first signal processor from a scan chain of the first signal processor, and receiving the internal state of the second signal processor from a scan chain of the second signal processor.
15. The method of claim 13 , wherein comparing the internal state of the first signal processor and the internal state of the second signal processor includes generating a state signature value for the first signal processor , and generating a state signature value for the second signal processor.
16. The method of claim 13 , further comprising:
transitioning the system to a safe state in response to determining that the mismatching internal state between the first and second signal processors, and thereby the mismatch between outputs, is not caused by a transient fault.