System and method for setting counter threshold value
View Patent ↗A system and method for configuring threshold values for fixed time delay counters of a System on a Chip (SoC) uses a reference clock signal and one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal. A frequency sub-range of the reference clock signal is determined using the frequency sub-range control signals and the determined frequency sub-range is used to select a counter threshold value. The selected counter threshold value is provided to a counter and the counter then is updated at each cycle of the reference clock signal for a predetermined count based on the counter threshold value.
1. A system for setting a counter threshold value, comprising:
a memory for storing one or more counter threshold values;
a multiplexer, connected to the memory, for selecting a counter threshold value from the one or more counter threshold values based on the frequency of a reference clock signal; and
a counter, connected to the multiplexer, that receives the selected counter threshold value from the multiplexer, wherein the counter is updated at each cycle of the reference clock signal for a predetermined count based on the selected counter threshold value.
2. The system for setting a counter threshold value of claim 1 , wherein updating the counter comprises incrementing the counter at each cycle of the reference clock signal.
3. The system for setting a counter threshold value of claim 1 , wherein updating the counter comprises decrementing the counter at each cycle of the reference clock signal.
4. The system for setting a counter threshold value of claim 1 , wherein the counter is a system on a chip (SoC) reset sequence counter.
5. The system of setting a counter threshold value of claim 4 , wherein the counter provides a phase locked loop (PLL) locking time for a system on a chip (SoC) reset sequence during SoC testing.
6. The system of setting a counter threshold value of claim 5 , wherein the SoC testing uses at least one of joint test action group (JTAG) patterns, memory built-in self test (MBIST) patterns, scan patterns, on die measurement (ODM) patterns, core expose patterns, interface electrical characterization patterns, and functional test patterns.
7. The system for setting a counter threshold value of claim 4 , further comprising:
a frequency range sampler, connected to the multiplexer, for determining a frequency sub-range of the reference clock signal, wherein the frequency range sampler receives one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal, samples the one or more frequency sub-range control signals to determine the frequency sub-range of the reference clock signal, and generates a code based on the determined frequency sub-range of the reference clock signal.
8. The system for setting a counter threshold value of claim 7 , wherein the multiplexer selects the counter threshold value based on the code.
9. A system for setting a threshold value of a reset sequence counter, the system comprising:
a memory for storing one or more counter threshold values;
a multiplexer, connected to the memory, for selecting a counter threshold value from the one or more counter threshold values based on the frequency of a reference clock signal;
a counter, connected to the multiplexer, that receives the selected counter threshold value from the multiplexer, wherein the counter is updated at each cycle of the reference clock signal for a predetermined count based on the selected counter threshold value; and
a frequency range sampler, connected to the multiplexer, for determining a frequency sub-range of the reference clock signal, wherein the frequency range sampler receives one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal, samples the one or more frequency sub-range control signals to determine the frequency sub-range of the reference clock signal, and generates a code based on the determined frequency sub-range of the reference clock signal, and wherein the multiplexer selects the counter threshold value based on the code.
10. A method of setting a counter threshold value, comprising:
receiving a reference clock signal;
receiving one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal;
determining the frequency sub-range of the reference clock signal using the one or more frequency sub-range control signals;
selecting a counter threshold value from one or more counter threshold values based on the frequency sub-range of the reference clock signal; and
providing the counter threshold value to a counter, wherein the counter is updated at each cycle of the reference clock signal for a predetermined count based on the counter threshold value.
11. The method of setting a counter threshold value of claim 10 , wherein updating the counter comprises incrementing the counter at each cycle of the reference clock signal.
12. The system of setting a counter threshold value of claim 10 , wherein updating the counter comprises decrementing the counter at each cycle of the reference clock signal.
13. The system of setting a counter threshold value of claim 10 , wherein the one or more counter threshold values are stored in one or more memory cells.
14. The method of setting a counter threshold value of claim 10 , wherein the counter is a SoC reset sequence counter that provides a phase locked loop (PLL) locking time for a system on a chip (SoC) reset sequence during SoC testing.
15. The system of setting a counter threshold value of claim 14 , wherein the SoC testing uses at least one of joint test action group (JTAG) patterns, memory built-in self test (MBIST) patterns, scan patterns, on die measurement (ODM) patterns, interface electrical characterization patterns, functional test patterns, and core expose patterns.
16. The method of setting a counter threshold value of claim 10 , wherein determining the frequency sub-range of the reference clock signal comprises sampling the one or more frequency sub-range control signals.
17. The method of setting a counter threshold value of claim 16 , further comprising generating a code corresponding to the determined frequency sub-range of the reference clock signal.
18. The method of setting a counter threshold value of claim 17 , wherein selecting a counter threshold value comprises selecting the counter threshold value based on the code.