IP Library Granted Patent US 8,775,699
Granted Patent B2
US 8,775,699 · App. 13/038,054 · Granted Jul 8, 2014

Read stacking for data processor interface

Inventors: Thang Q. Nguyen (Austin, TX); Gus P. Ikonomopoulos (Lakeway, TX)
Assignee: Freescale Semiconductor, Inc.
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Quick Facts
Patent No.
US 8,775,699
App. No.
13/038,054
Granted
Jul 8, 2014
Kind
B2
Abstract

A gasket of a data processing device controls the number of released storage locations of a buffer where read and write access requests are stored so that more read access requests can be stored without a corresponding increase in the amount of space at the buffer to store write access requests. An interface of the gasket accepts new access requests from one or more requesting modules only when a number of released storage locations at a buffer associated with the interface (referred to as an outbound buffer) is above a threshold number. As long as the number of stored access requests at the outbound buffer are less than a threshold amount, a buffer location can be immediately released. In addition, the gasket is configured to issue read access requests from the outbound buffer without regard to whether the inbound buffer has space available.

Claims (55)

1. In a data processing device, a method comprising:

in response to receiving access requests that are requests to transfer information via an interface module, adjusting a count of a number of released buffer spaces at an outbound request buffer from an initial amount to an adjusted amount, the initial amount based on a maximum number of write access requests that can be stored at the outbound request buffer at the same time and storing the access requests at the outbound request buffer;

in response to determining the number of released buffer spaces at the outbound request buffer is less than a first threshold amount, communicating an indication from the interface module that write access requests and read access requests are not to be communicated to the interface module; and

storing at the outbound request buffer a set of access requests, the number of access requests in the set greater than the maximum number of write access requests that can be stored at the outbound request buffer.

2. The method of claim 1 , further comprising:

decrementing the number of released buffer spaces in response to receiving a first access request at the interface module;

in response to determining the first access request is a read access request, storing the first access request at the outbound request buffer and incrementing the number of released buffer spaces prior to receiving an indication at the interface module that the first access request is complete.

3. The method of claim 2 , further comprising:

in response to determining the first access request is a write access request, incrementing the number of released buffer spaces in response to receiving the indication at the interface module that the first access request is complete.

4. The method of claim 1 , further comprising:

decrementing the number of released buffer spaces in response to receiving a first access request at the interface module;

in response to determining the first access request is a read access request:

storing the first access request at the outbound request buffer and incrementing the number of released buffer spaces prior to receiving an indication at the interface module that the first access request is complete in response to determining that a number of storage locations available to store the read access request is greater than a second threshold amount.

5. The method of claim 4 , further comprising:

in response to determining the first access request is a read access request, incrementing the number of released buffer spaces prior to receiving an indication at the interface module that the first access request is complete in response to determining that a number of write access requests stored at the outbound request buffer is less than the second threshold amount.

6. The method of claim 5 , wherein incrementing the number of released buffer spaces comprises incrementing the number of released buffer spaces in response to determining the read access request is associated with a prefetchable memory location.

7. The method of claim 1 , further comprising receiving the access requests from one or more processor cores.

8. The method of claim 1 , further comprising:

issuing a first occurrence of a read access request to request first data;

in response to receiving the first data and determining space is available at an inbound data buffer, storing the first data at the inbound data buffer; and

in response to receiving the first data and determining space is not available at the inbound data buffer:

discarding the first data; and

issuing a second occurrence of the read access request.

9. At a data processing device, a method comprising:

issuing a first occurrence of a read access request from an interface module of the data processing device;

receiving first data at the interface module in response to the first occurrence of the first read access request;

storing the first data at an inbound data buffer of the interface module in response to determining space is available at the inbound data buffer;

discarding the first data at the interface module in response to determining space to store the first data is not available;

adjusting a number of discarded data responses in response to discarding the first data; and

in response to the number of discarded data responses being greater than a threshold number, issuing a second occurrence of the first read access request in response to determining space is available at the inbound data buffer to store the first data.

10. The method of claim 9 , wherein issuing the second occurrence of the first read access request further comprises:

in response to determining the number of discarded data responses is not greater than the threshold number, issuing the second occurrence of the first read access request for the second time without determining whether space is available at the inbound data buffer to store the first data.

11. The method of claim 9 , further comprising determining space is available for the first data in response to determining a location of the inbound data buffer where the first data is to be stored is in the process of being flushed of previously stored data.

12. A data processing device, comprising:

an outbound request buffer to store a maximum number of access requests that are requests to transfer information via a gasket, the maximum number of access requests greater than a maximum number of write access requests that can be stored at the outbound request buffer at the same time; and

an interface coupled to the outbound request buffer, the interface comprising:

an input to receive the access requests;

a first counter to store a value indicating a number of released buffer spaces at the outbound request buffer, the first counter to adjust the value from an initial amount to an adjusted amount in response to receiving the access requests, the initial amount based on the maximum number of write access requests that can be stored at the outbound request buffer; and

the interface to, in response to determining the value stored at the counter is less than a first threshold amount, communicate an indication that access requests are not to be communicated to the gasket.

13. The data processing device of claim 12 , wherein the interface:

decrements the value stored at the first counter in response to receiving a first access request at the interface module; and

in response to determining the first access request is a read access request, stores the first access request at the outbound request buffer and increment the value stored at the first counter prior to receiving an indication at the gasket that the first access request is complete.

14. The data processing device of claim 13 , wherein the interface, in response to determining the first access request is a write access request, increments the value stored at the first counter in response to receiving an indication that the first access request is complete.

15. The data processing device of claim 14 , wherein the interface:

decrements the value stored at the first counter in response to receiving the first access request at the gasket; and

in response to determining the first access request is a read access request:

stores the first access request at the outbound request buffer and increment the value stored at the first counter prior to receiving an indication at the gasket that the first access request is complete in response to determining a number of storage locations at the outbound request buffer available to store the first access request is greater than a second threshold amount.

16. The data processing device of claim 15 , wherein the interface increments the value stored at the first counter in response to determining a number of write access requests stored at the outbound request buffer is less than a third threshold amount.

17. The data processing device of claim 12 , wherein the interface:

in response to determining the first access request is a read access request, issues a first occurrence of the read access request;

receives first data in response to the first occurrence of the read access request;

stores the first data at an inbound data buffer in response to determining space is available at the inbound data buffer;

discards the first data at the gasket in response to determining space to store the first data is not available at the inbound data buffer; and

issues a second occurrence of the read access request in response to discarding the first data.

18. The data processing device of claim 12 , wherein the interface is coupled to a peripheral component interconnect express (PCIE) interface.

Assignments (32)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2021
From: NXP B.V.
To: FUTURE LINK SYSTEMS, LLC
Reel/Frame 055115/0491 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
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To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
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SECURITY AGREEMENT Recorded Nov 6, 2013
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SECURITY AGREEMENT Recorded Jan 31, 2012
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SECURITY AGREEMENT Recorded Jan 31, 2012
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SECURITY AGREEMENT Recorded Jan 31, 2012
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