Process of forming an electronic device including insulating layers having different strains
View Patent ↗An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
1. A process of forming an electronic device comprising:
forming a field isolation region within a substrate to define a first active region and a second active region, wherein:
the first active region lies immediately adjacent to the field isolation region; and
the second active region lying immediately adjacent to the field isolation region and is spaced apart from the first active region;
forming a p-channel transistor within the first active region;
forming an n-channel transistor within the second active region;
forming a first insulating layer over the field isolation region and having a first strain, wherein from a top view, an island portion of the first insulating layer lies entirely within the field isolation region, and wherein a second portion of the first insulating layer overlies the p-channel transistor; and
forming a second insulating layer over the field isolation region, having a second strain different from the first strain, and including a first opening, wherein from a top view, the island portion of the first insulating layer lies within the first opening in the second insulating layer, and wherein the second insulating layer overlies the n-channel transistor.
2. The process of claim 1 , wherein forming the island portion includes forming the island portion more than approximately 2 microns from the first active region.
3. The process of claim 1 , wherein:
the first strain is a compressive strain; and
the second strain is a tensile strain.
4. The process of claim 3 , wherein:
forming the first insulating layer includes using a set of precursor chemicals; and
forming the second insulating layer includes using a different set of precursor materials.
5. The process of claim 3 , wherein forming the second insulating layer is performed at a particular radio frequency (“RF”) and a particular RF power.
6. The process of claim 5 , wherein forming the first insulating layer is performed at a different RF as compared to forming the second insulating layer or at a different RF power as compared to forming the second insulating layer.
7. The process of claim 3 , wherein forming the first insulating layer and forming the second insulating layer occur at different points in time.
8. The process of claim 1 , wherein:
forming the p-channel transistor is performed before forming the first insulating layer; and
forming the n-channel transistor is performed before forming the second insulating layer.
9. The process of claim 8 , further comprising:
removing a portion of the first insulating layer from over the p-channel transistor; and
removing a portion of the second insulating layer from over the n-channel transistor.
10. The process of claim 8 , further comprising:
forming a third insulating layer over the first insulating layer and the second insulating layer;
etching a first contact opening through the third insulating layer and stopping on the first insulating layer;
etching the first insulating layer within the first opening;
etching a second contact opening through the third insulating layer and stopping on the second insulating layer;
etching the second insulating layer within the second contact opening;
forming a first contact within the first contact opening, wherein the first contact is electrically connected to the p-channel transistor; and
forming a second contact within the second contact opening, wherein the second contact is electrically connected to the n-channel transistor.
11. A process of forming an electronic device comprising:
forming a field isolation region overlying a substrate to define an active region, wherein the field isolation region includes:
a first dummy structure including a first portion of the substrate; and
a second dummy structure including a second portion of the substrate;
forming a first insulating layer overlying the first dummy structure and not the second dummy structure, wherein the first insulating layer has a first strain; and
forming a second insulating layer overlying the second dummy structure and not the first dummy structure, wherein the second insulating layer has a second strain different from the first strain, and from a top view:
the first insulating layer lies within an opening in the second insulating layer; and
substantially none of the active region lies within the opening.
12. The process of claim 11 , wherein forming the field isolation region is performed such that a shortest distance from the first dummy structure to the active region is longer than a shortest distance from the second dummy structure to the active region.
13. The process of claim 11 , wherein forming the first insulating layer and forming the second insulating layer is performed such that the first insulating layer and the second insulating layer have a substantially same chemical composition.
14. The process of claim 11 , wherein:
the first strain is a compressive strain; and
the second strain is a tensile strain.
15. The process of claim 14 , wherein:
forming the first insulating layer includes using a set of precursor chemicals; and
forming the second insulating layer includes using a different set of precursor materials.
16. The process of claim 14 , wherein forming the second insulating layer is performed at a particular radio frequency (“RF”) and a particular RF power.
17. The process of claim 16 , wherein forming the first insulating layer is performed at a different RF as compared to forming the second insulating layer or at a different RF power as compared to forming the second insulating layer.
18. The process of claim 14 , wherein:
the process further comprises forming a p-channel transistor within the active region;
forming the field isolation defines another active region; and
the process further comprises forming an n-channel transistor within the other active region.
19. The process of claim 18 , further comprising:
removing a portion of the first insulating layer from over the p-channel transistor; and
removing a portion of the second insulating layer from over the n-channel transistor.
20. The process of claim 19 , further comprising removing another portion of the second insulating layer from over the first dummy structure.