Process of forming an electronic device including a conductive stud over a bonding pad region
View Patent ↗An electronic device can include an interconnect level including a bonding pad region. An insulating layer can overlie the interconnect level and include an opening over the bonding pad region. In one embodiment, a conductive stud can lie within the opening and can be substantially encapsulated. In another embodiment, the electronic device can include a barrier layer lying along a side and a bottom of the opening and a conductive stud lying within the opening. The conductive stud can substantially fill the opening. A majority of the conductive stud can lie within the opening. In still another embodiment, a process for forming an electronic device can include forming a conductive stud within the opening wherein from a top view, the conductive stud lies substantially completely within the opening. The process can also include forming a second barrier layer overlying the conductive stud.
1. A process of forming an electronic device comprising:
forming an interconnect level over a substrate, wherein the interconnect level further includes a bonding pad region;
forming an insulating layer overlying the interconnect level;
forming an opening in the insulating layer to expose the bonding pad region;
forming a first barrier layer within the opening;
forming a conductive stud within the opening, wherein from a top view, substantially all of the conductive stud lies within the opening; and
forming a second barrier layer overlying the conductive stud, wherein the conductive stud is substantially encapsulated by the first and second barrier layers; and forming a solder bump over the second barrier layer, the conductive stud, and the bonding pad region of the interconnect level, wherein the solder bump is spaced apart from the conductive stud and the bonding pad region of the interconnect level.
2. The process of claim 1 , further comprising forming a seed layer after forming the first barrier layer.
3. The process of claim 2 , wherein forming the conductive stud comprises plating a conductive layer.
4. The process of claim 3 , wherein forming the conductive stud comprises:
forming a sacrificial layer including an opening over the bonding pad region prior to plating the a conductive layer;
removing the sacrificial layer after plating the conductive layer; and
removing exposed portions of the first barrier layer and the seed layer after plating the conductive layer.
5. The process of claim 4 , wherein removing the exposed portions of the first barrier layer includes using a chemical mechanical polishing process.
6. The process of claim 1 , further comprising forming a passivation layer including an opening over the bonding pad region, after forming the conductive stud, and prior to forming the second barrier layer.
7. The process of claim 1 , wherein the second barrier layer is a part of an under-bump metallization layer immediately adjacent to the conductive stud.
8. The process of claim 1 , wherein forming the solder bump is performed such that substantially none of the solder bump lies within the opening of the insulating layer.
9. The process of claim 8 , wherein forming the second barrier layer is performed such that substantially none of the second barrier layer lies within the opening of the insulating layer.
10. The process of claim 1 , wherein:
forming the second barrier layer is part of forming an under-bump metallization layer having uppermost and side surfaces, wherein the bonding pad region is farther from the uppermost surface than the side surface; and
forming the solder bump is performed such that the solder bump abuts the side surface of the underbump metallization layer at a location that does not overlie the conductive stud.
11. A process for forming an electronic device comprising:
forming an interconnect level including a bonding pad region;
forming an insulating layer overlying the interconnect level and including an opening over the bonding pad region;
forming a conductive stud lying within the opening over the bonding pad region, wherein substantially all of the conductive stud lies within the opening;
forming a barrier layer over the conductive stud; and
forming a solder bump over the barrier layer, the conductive stud, and the bonding pad region of the interconnect level, wherein the solder bump is spaced apart from the conductive stud and the bonding pad region of the interconnect level.
12. The process of claim 11 , wherein forming the insulating layer includes forming a nitride layer.
13. The process of claim 11 , wherein forming the solder bump is performed such that substantially none of the solder bump lies within the opening of the insulating layer.
14. The process of claim 13 , wherein forming the barrier layer is performed such that substantially none of the barrier layer lies within the opening of the insulating layer.
15. The process of claim 11 , wherein:
forming the barrier layer is part of forming an underbump metallization layer having uppermost and side surfaces, wherein the bonding pad region is farther from the uppermost surface than the side surface; and
forming the solder bump is performed such that the solder bump abuts the side surface of the underbump metallization layer at a location that does not overlie the conductive stud.
16. The process of claim 11 , further comprising forming a seed layer after forming the first barrier layer.
17. The process of claim 16 , wherein forming the conductive stud comprises plating a conductive layer.
18. The process of claim 17 , wherein forming the conductive stud comprises plating Ag, Au, Cu, Pt, or any combination thereof.
19. The process of claim 17 , wherein forming the conductive stud comprises plating Cu.
20. The process of claim 1 , wherein from the top view all of the conductive stud lies within the opening.