Methods and apparatus for testing multiple-IC devices
View Patent ↗Embodiments include systems that include at least one integrated circuit (IC) and methods for their testing. Each IC includes an input interconnect to receive an input signal, a test enable interconnect to receive a test enable signal, and a controller (e.g., a TAP controller) for performing testing of the integrated circuit based on values in at least one register (values corresponding to the input signal). Each IC also includes an input port and a multiplexer coupled to the first input interconnect, the at least one register, and the input port. The multiplexer is controllable to pass the input signal to the input port in response to non-assertion of the test enable signal, and to pass the input signal to the at least one register in response to assertion of the test enable signal. When the system includes multiple controllers, each controller may implement a different opcode-to-instruction mapping.
1. An integrated circuit comprising:
a first input interconnect configured to receive an input signal;
a first test enable interconnect configured to receive a test enable signal;
a controller for performing testing of the integrated circuit based on values that correspond to the input signal;
an input port;
a first multiplexer coupled to the first input interconnect, the controller, and the input port, and controllable to pass the input signal to the input port in response to non-assertion of the test enable signal, and to pass the input signal to the controller in response to assertion of the test enable signal;
a first test data out interconnect configured to produce test output data;
a second test data out interconnect configured to receive remotely-produced test output data;
a register configured to store an indication that the integrated circuit is or is not in a boundary scan pass-through mode;
a second multiplexer coupled to the first test data out interconnect, and controllable to pass first test output data produced by the integrated circuit to the first test data out interconnect to be produced as the test output data when the integrated circuit is not in the boundary scan pass-through mode; and
a third multiplexer coupled to the second test data out interconnect and to the second multiplexer, and controllable to pass the remotely-produced test output data to the second multiplexer to be produced as the test output data on the first test data out interconnect when the integrated circuit is in the boundary scan pass-through mode.
2. The integrated circuit of claim 1 , wherein:
the input port is selected from a group consisting of an inter-integrated circuit (I2C) port and a serial peripheral interface (SPI) port.
3. The integrated circuit of claim 1 , further comprising:
a first output interconnect configured to produce an output signal; and
a fourth multiplexer coupled to the first output interconnect and to the first input interconnect, and controllable in response to assertion of the test enable signal to pass the input signal to the first output interconnect to be produced as the output signal.
4. The integrated circuit of claim 3 , further comprising:
an output port coupled to the fourth multiplexer and configured to produce output port signals, wherein the fourth multiplexer is controllable in response to non-assertion of the test enable signal to pass the output port signals to the first output interconnect to be produced as the output signal.
5. The integrated circuit of claim 4 , wherein the output port is selected from a group consisting of an inter-integrated circuit (I2C) port, a serial peripheral interface (SPI) port, and a dual-mode I2C/SPI port.
6. The integrated circuit of claim 1 , further comprising:
a second test enable interconnect configured to produce the test enable signal as an output signal.
7. The integrated circuit of claim 1 , further comprising:
a reset interconnect configured to receive an external reset signal; and
a reset circuit coupled to the reset interconnect, and configured to produce an output reset signal corresponding to the external reset signal in response to assertion of the test enable signal.
8. The integrated circuit of claim 1 , further comprising:
an external clock interconnect configured to receive an external clock signal; and
a clock circuit coupled to the external clock interconnect, and configured to produce an output clock signal corresponding to the external clock signal in response to assertion of the test enable signal.
9. A method of operating an integrated circuit comprising:
receiving, by, a first input interconnect, an input signal;
receiving, by a first test enable interconnect, a test enable signal;
performing, by a controller, testing of the integrated circuit based on values that correspond to the input signal;
passing, by a first multiplexer, the input signal to an input port in response to non-assertion of the test enable signal, and to passing the input signal to the controller in response to assertion of the test enable signal;
producing, by a first test data out interconnect, test output data;
receiving, by a second test data out interconnect, remotely-produced test output data;
setting, in a register, an indication of whether the integrated circuit is or is not in a boundary scan pass-through mode;
passing, by a second multiplexer, first test output data produced by the integrated circuit to the first test data out interconnect to be produced as the test output data when the integrated circuit is not in the boundary scan pass-through mode; and
passing, by a third multiplexer, the remotely-produced test output data to the second multiplexer to be produced as the test output data on the first test data out interconnect when the integrated circuit is in the boundary scan pass-through mode.
10. The method of claim 9 , further comprising:
producing, by a first output interconnect, an output signal; and
passing, by a fourth multiplexer, the input signal to the first output interconnect in response to assertion of the test enable signal to be produced as the output signal.
11. The method of claim 10 , further comprising:
producing output port signals by an output port, wherein the fourth multiplexer is controllable in response to non-assertion of the test enable signal to pass the output port signals to the first output interconnect to be produced as the output signal.
12. The method of claim 9 , further comprising:
producing, by a second test enable interconnect, the test enable signal as an output signal.
13. The method of claim 9 , further comprising:
receiving, by a reset interconnect, an external reset signal; and
producing, by a reset circuit, an output reset signal corresponding to the external reset signal in response to assertion of the test enable signal.
14. The method of claim 9 , further comprising:
receiving, by an external clock interconnect, an external clock signal; and
producing, by a clock circuit, an output clock signal corresponding to the external clock signal in response to assertion of the test enable signal.