Method of forming a shared contact in a semiconductor device
View Patent ↗A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor and a source/drain region corresponding to a second transistor is provided. The method includes forming a first opening in a dielectric layer overlying the gate electrode and the source/drain region, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor. The method further includes after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the source/drain region corresponding to the second transistor. The method further includes forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material.
1. A method for forming a shared contact in a semiconductor device having a gate electrode corresponding to a first transistor, a source/drain region corresponding to a second transistor, and a shallow trench isolation region extending from an edge of the source/drain region closest to the gate electrode to at least under the gate electrode, wherein the gate electrode corresponding to the first transistor, the source/drain region corresponding to the second transistor, and at least a portion of the shallow trench isolation region have an overlying dielectric layer, the method comprising:
forming a first opening in the overlying dielectric layer, wherein the first opening extends substantially to the gate electrode corresponding to the first transistor;
after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein
the second opening extends substantially to the source/drain region corresponding to the second transistor, and
the second opening is aligned to avoid being over the shallow trench isolation region; and
forming the shared contact between the gate electrode corresponding to the first transistor and the source/drain region corresponding to the second transistor by filling the first opening and the second opening with a conductive material.
2. The method of claim 1 , wherein the first opening has a first width and a first depth and the second opening has a second width and a second depth, and wherein the first width is greater than the second width and the first depth is lower than the second depth.
3. The method of claim 1 further comprising:
prior to filling the first opening and the second opening with the conductive material, forming a glue layer in the first opening and the second opening.
4. The method of claim 1 , wherein the gate electrode comprises a first portion and a second portion, wherein the second portion is silicided, and wherein a spacer is formed adjacent to both the first portion and the second portion of the gate electrode, and wherein forming the second opening further comprises:
etching the overlying dielectric layer such that a minimal portion of the spacer adjacent to the first portion of the gate electrode is etched.
5. The method of claim 1 , wherein the step of forming the first opening comprises patterning and etching a first portion of the overlying dielectric layer using a first mask.
6. The method of claim 5 , wherein the step of forming the second opening comprises patterning and etching a second portion of the overlying dielectric layer using a second mask different from the first mask.
7. The method of claim 6 , wherein the semiconductor device further comprises a nitride layer formed below the overlying dielectric layer, wherein the step of patterning and etching the first portion of the overlying dielectric layer using the first mask further comprises etching a first portion of the nitride layer, and wherein the step of patterning and etching the second portion of the overlying dielectric layer using the second mask further comprises etching a second portion of the nitride layer.
8. A method for forming a shared contact in a semiconductor device having a source/drain region corresponding to a first transistor, a gate electrode corresponding to a second transistor, and a shallow trench isolation region extending from an edge of the source/drain region of the first transistor closest to the gate electrode of the second transistor to at least under the gate electrode of the second transistor, wherein the source/drain region corresponding to the first transistor and the gate electrode corresponding to the second transistor have an overlying dielectric layer, the method comprising:
forming a first opening in the overlying dielectric layer, wherein
the first opening extends substantially to the source/drain region corresponding to the first transistor, and
the first opening is aligned to avoid being over the shallow trench isolation region;
after forming the first opening, forming a second opening, contiguous with the first opening, in the overlying dielectric layer, wherein the second opening extends substantially to the gate electrode corresponding to the second transistor; and
forming the shared contact between the source/drain region corresponding to the first transistor and the gate electrode corresponding to the second transistor by filling the first opening and the second opening with a conductive material.
9. The method of claim 8 , wherein the first opening has a first width and a first depth and the second opening has a second width and a second depth, and wherein the first width is lower than the second width and the first depth is greater than the second depth.
10. The method of claim 8 further comprising:
prior to filling the first opening and the second opening with the conductive material, forming a glue layer in the first opening and the second opening.
11. The method of claim 8 , wherein the gate electrode comprises a first portion and a second portion, wherein the second portion is silicided, and wherein a spacer is formed adjacent to both the first portion and the second portion of the gate electrode, and wherein forming the first opening further comprises:
etching the overlying dielectric layer such that a minimal portion of the spacer adjacent to the first portion of the gate electrode is etched.
12. The method of claim 8 , wherein the step of forming the first opening comprises patterning and etching a first portion of the overlying dielectric layer using a first mask.
13. The method of claim 12 , wherein the step of forming the second opening comprises patterning and etching a second portion of the overlying dielectric layer using a second mask different from the first mask.
14. The method of claim 13 , wherein the semiconductor device further comprises a nitride layer formed below the overlying dielectric layer, wherein the step of patterning and etching the first portion of the overlying dielectric layer using the first mask further comprises etching a first portion of the nitride layer, and wherein the step of patterning and etching the second portion of the overlying dielectric layer using the second mask further comprises etching a second portion of the nitride layer.
15. The method of claim 8 further comprising: prior to forming the second opening, forming a photoresist layer above the overlying dielectric layer and etching the photoresist layer to leave a portion of the photoresist layer inside at least a bottom portion of the first opening.
16. A method for forming a shared contact in a semiconductor device having a source/drain region corresponding to a first transistor and a gate electrode corresponding to a second transistor, wherein the source/drain region corresponding to the first transistor and the gate electrode corresponding to the second transistor have an overlying dielectric layer, the method comprising:
forming a first opening in the overlying dielectric layer, wherein the first opening extends substantially to the source/drain region corresponding to the first transistor;
forming a first glue layer in the first opening;
after forming the first glue layer in the first opening and filling the first opening with a conductive material, forming a second opening, wherein the second opening has one side adjacent to the first glue layer, in the overlying dielectric layer, wherein the second opening extends substantially to the gate electrode corresponding to the second transistor; and
forming a second glue layer in the second opening and filling the second opening with the conductive material to form the shared contact between the source/drain region of the first transistor and the gate electrode of the second transistor.
17. The method of claim 16 , wherein the first opening has a first width and a first depth and the second opening has a second width and a second depth, and wherein the first width is lower than the second width and the first depth is greater than the second depth.
18. The method of claim 16 , wherein the gate electrode comprises a first portion and a second portion, wherein the second portion is silicided, and wherein a spacer is formed adjacent to both the first portion and the second portion of the gate electrode, and wherein forming the first opening further comprises:
etching the overlying dielectric layer such that a minimal portion of the spacer adjacent to the first portion of the gate electrode is etched.
19. The method of claim 16 , wherein the step of forming the first opening comprises patterning and etching a first portion of the overlying dielectric layer using a first mask.
20. The method of claim 19 , wherein the step of forming the second opening comprises patterning and etching a second portion of the overlying dielectric layer using a second mask different from the first mask.