Control of interrupt generation for cache
View Patent ↗A data processing device includes a cache having a plurality of cache lines. Each cache line has a lockout state that indicates whether an error has been detected for data accessed at the cache line. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. When a cache line is in a locked-out state, the cache line is not used by the cache. Accordingly, a locked-out cache line is not employed by the cache to satisfy a cache accesses, and is not used to store data retrieved from memory in response to a cache miss. In response to determining the detected error likely did not result from a hardware failure or other persistent condition, memory error management software can reset the lockout state of the cache line.
1. In a data processing device comprising a processor unit coupled to a cache comprising a plurality of cache lines, a method comprising:
in response to a first cache access to a first cache line of the plurality of cache lines:
when a lockout policy for the cache is a first policy, generating an interrupt at the data processing device and setting a lockout indicator to a first state in response to detecting a first error in information stored at the first cache line; and
when the lockout policy for the cache is a second policy, responding to the first cache access without generating the interrupt, and setting the lockout indicator to the first state in response to detecting the first error; and
in response to a second cache access to the first cache line, preventing the first cache line from satisfying the second cache access when the lockout indicator is in the first state.
2. The method of claim 1 , further comprising:
when the lockout policy for the cache is a third policy, responding to the first cache access without generating the interrupt and maintaining the lockout indicator in a second state in response to detecting the first error.
3. The method of claim 1 , further comprising:
when the lockout policy is a third policy:
generating an interrupt at the data processing device in response to detecting the first error; and
setting the lockout indicator to the first state in response to determining the first error is an uncorrectable error.
4. The method of claim 3 , wherein determining the error is an uncorrectable error comprises determining the first error is a multi-bit error.
5. The method of claim 3 , further comprising:
when the lockout policy is the third policy:
maintaining the lockout indicator in a second state in response to determining the first error is a correctable error;
recycling the access in response to detecting the first error; and
setting the lockout indicator in response to detecting a second error in response to the recycled access.
6. The method of claim 5 , wherein the first error comprises an error in tag information associated with the first cache line.
7. The method of claim 1 wherein further comprising satisfying the second cache access from the first cache line when the lockout indicator is in the second state.
8. The method of claim 1 , further comprising determining the lockout policy based on information stored at a register.
9. The method of claim 1 , wherein the first error comprises an error at tag information associated with the first cache line.
10. The method of claim 1 , wherein the first error comprises an error at data stored at the first cache line, the data different from tag information associated with the first cache line.
11. The method of claim 1 , wherein the lockout indicator comprises a plurality of redundant indicators.
12. A method, comprising:
in response to receiving a cache access comprising a read access or a write access at a cache, determining a lockout policy for the cache;
in response to determining the lockout policy is a first policy, generating an interrupt and setting a lockout indicator to a first state when a first error is detected in response to the cache access;
in response to determining the lockout policy is a second policy, responding to the cache access without generating the interrupt and setting the lockout indicator to the first state when the first error is detected; and
determining whether to indicate a cache hit based on the state of the lockout indicator.
13. The method of claim 12 , further comprising:
in response to determining the lockout policy is a third policy, maintaining the lockout indicator in a second state in response to detecting the first error.
14. The method of claim 12 , wherein responding to the cache access comprises indicating an error was detected to a processor unit.
15. The method of claim 12 wherein the interrupt comprises a machine check interrupt.
16. A device, comprising:
a processor unit;
a cache comprising a plurality of cache lines including a first cache line; and
a cache control module configured to, when a lockout policy is a first policy, set a state of a lockout indicator for the first cache line to a first state and generate an interrupt when a first error is detected based on a cache access, and when the lockout policy is a second policy, set the state of the lockout indicator to the first state without generating the interrupt when the first error is detected based on the cache access;
the cache control module configured to prevent the first cache line from satisfying cache accesses when the lockout indicator is in the first state.
17. The device of claim 16 , wherein the cache control module is configured to, in response to determining the lockout policy for the cache is a third policy, respond to the cache access without generating the interrupt and maintain the lockout indicator in a second state in response to detecting the first error.
18. The device of claim 16 , wherein the cache control module is configured to, in response to determining the lockout policy for the cache is a third policy:
generate an interrupt at the data processing device in response to detecting the first error; and
set the lockout indicator to the first state in response to determining the first error is an uncorrectable error.
19. The device of claim 16 , wherein the cache control module is configured to determines the first error is an uncorrectable error comprises in response to determining the first error is a multi-bit error.
20. The device of claim 16 , wherein the cache control module comprises an error detection and correction module configured to detect the first error.