Surface treatment in semiconductor manufacturing
View Patent ↗The present invention provides a process for forming a capping layer on a conducting interconnect for a semiconductor device, the process comprising: providing a substrate comprising one or more conductors in a dielectric layer, the conductors having an oxide layer at their surface; exposing the surface of the substrate to a vapor of β-diketone or a β-ketoimine; and depositing a capping layer on the surface of at least some of the one or more conductors. The present invention further provides an apparatus for carrying out this method.
1. A process for forming a capping layer on a conducting interconnect for a semiconductor device, the process comprising:
(a) providing a substrate comprising one or more conductors in a dielectric layer, the conductors having an oxide layer at their surface;
(b) exposing the surface of the substrate to a vapour of β-diketone or β-ketoimine without cleaning the surface with an aqueous acidic solution having a pH of 4 or less following formation of the substrate comprising the one or more conductors having the oxide layer at their surface and prior to exposing; and
(c) depositing a capping layer on the surface of at least some of the one or more conductors.
2. The process of claim 1 , wherein the conductor comprises copper.
3. The process of claim 2 , wherein the oxide layer comprises an oxide of palladium.
4. The process of claim 2 , wherein the β-diketone is 1,1,1,5,5,5-hexafluoroacetylacetone.
5. The process of claim 2 , wherein step (b) is carried out in an atmosphere in which the metal is not oxidized.
6. The process of claim 1 , wherein the oxide layer comprises an oxide of palladium.
7. The process of claim 6 , wherein the β-diketone is 1,1,1,5,5,5-hexafluoroacetylacetone.
8. The process of claim 6 , wherein step (b) is carried out in an atmosphere in which the metal is not oxidized.
9. The process of claim 1 , wherein the β-diketone is 1,1,1,5,5,5-hexafluoroacetylacetone.
10. The process of claim 1 , wherein step (b) is carried out in an atmosphere in which the metal is not oxidized.
11. The method of claim 1 , wherein providing a substrate includes providing the substrate following chemical mechanic polishing (CMP) of the substrate.
12. The method of claim 1 , wherein exposing the surface of the substrate to a vapour includes exposing the surface to a vapour comprising β-ketoimine.
13. An apparatus for depositing a capping layer on a conducting interconnect, the apparatus comprising:
a chemical mechanical polishing device;
a first chamber having a support to support a substrate and a heater to heat a substrate placed on the support,
a source of β-diketone or β-ketoimine vapour,
a vacuum pump associated with said first chamber,
a second chamber for carrying out deposition of a capping layer;
the apparatus being adapted so that a substrate may be transferred from said first chamber to said second chamber in a non-oxidizing atmosphere; and
the apparatus being adapted so that the substrate may be transferred from said chemical mechanical polishing device to said first chamber without cleaning with an aqueous acidic solution having a pH of 4 or less.
14. The apparatus according to claim 13 , wherein the source of β-diketone or β-ketoimine vapour comprises a bubbler containing a liquid β-diketone or β-ketoimine connected to said first chamber, and a source of carrier gas connected to said bubbler.
15. The apparatus according to claim 14 , the apparatus further comprising a controller and instructions associated with the controller, wherein the instructions, when executed by the controller, exposes the surface of a substrate placed in the first chamber of the apparatus to a vapour of β-diketone or a β-ketoimine.
16. The apparatus according to claim 13 , the apparatus further comprising a controller and instructions associated with the controller, wherein the instructions, when executed by the controller, exposes the surface of a substrate placed in the first chamber of the apparatus to a vapour of β-diketone or a β-ketoimine.
17. A semiconductor device having conducting interconnects provided with a capping layer obtainable with a process comprising:
(a) providing a substrate comprising one or more conductors in a dielectric layer, the conductors having an oxide layer at their surface;
(b) exposing the surface of the substrate to a vapour of β-diketone or β-ketoimine without cleaning the surface with an aqueous acidic solution having a pH of 4 or less following formation of the substrate comprising the one or more conductors having the oxide layer at their surface and prior to exposing; and
(c) depositing a capping layer on the surface of at least some of the one or more conductors.
18. The device of claim 17 , wherein the conductor comprises copper.
19. The device of claim 17 , wherein the oxide layer comprises an oxide of palladium.
20. The device of claim 19 , wherein step (b) is carried out in an atmosphere in which the metal is not oxidized.
21. The device of claim 17 , wherein the β-diketone is 1,1,1,5,5,5-hexafluoroacetylacetone.
22. The device of claim 17 , wherein step (b) is carried out in an atmosphere in which the metal is not oxidized.
23. The semiconductor device of claim 17 , wherein providing a substrate includes providing the substrate following chemical mechanic polishing (CMP) of the substrate.
24. The semiconductor device of claim 17 , wherein exposing the surface of the substrate to a vapour includes exposing the surface to a vapour comprising β-ketoimine.