Programmable delay timer and method therefor
View Patent ↗A timer circuit, comprises a delay indication circuit, a frequency indication circuit, and a plurality of counters. The delay indication circuit is for providing a delay time indication. The frequency indication circuit is for providing a frequency indication of a frequency of a clock signal. Each counter of the plurality of counters includes a load input to receive an initial value, and an indication output to provide a count complete indication of the counter. During operation a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired. At least a portion of the frequency indication is provided to the load input of one counter of the set and at least a portion of the delay time indication is provided to the load input of another counter of the set.
1. A timer circuit, comprising:
a delay indication circuit, the delay indication circuit providing a delay time indication;
a frequency indication circuit, the frequency indication circuit providing a frequency indication of a frequency of a clock signal;
a clock input to receive the clock signal; and
a plurality of counters, wherein each counter of the plurality of counters includes a load input to receive an initial value and an indication output to provide a count complete indication of the counter, wherein during operation when a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired, at least a portion of the frequency indication is provided to the load input of one counter of the set and at least a portion of the delay time indication is provided to the load input of another counter of the set.
2. The timer circuit of claim 1 wherein the frequency indication includes a first portion and a second portion, wherein the first portion of the frequency indication is selectably providable to a load input of a counter of the plurality of counters based on the second portion of the frequency indication.
3. The timer circuit of claim 2 wherein the first portion of the frequency indication is selectably providable to a load input of a second counter of the plurality of counters based on the second portion of the frequency indication.
4. The timer circuit of claim 2 wherein:
the plurality of counters is couplable in series; and
for an initial in series counter of the plurality of counters, the load input is coupled to the frequency indication circuit to receive the first portion of the frequency indication.
5. The timer circuit of claim 1 wherein:
the plurality of counters is couplable in series; and
each subsequent counter of the plurality of counters couplable in the series includes an input to selectably receive, based on a portion of the frequency indication, a count complete indication from the indication output of a preceding counter of the plurality of counters couplable in the series.
6. The timer circuit of claim 1 wherein:
when a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired, a first portion of the delay indication is provided to the load input of the another counter; and
the another counter is selected from the plurality of counters based upon a second portion of the delay time indication.
7. The timer circuit of claim 6 wherein the first portion of the delay time indication indicates a numerical value of a delay time and the second portion of the delay time indication indicates a unit of time of the delay time.
8. The timer circuit of claim 1 wherein when a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired, the indication output of the another counter provides an indication that a delay time has expired.
9. The timer circuit of claim 1 wherein when a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired, at least the one counter receives the clock signal at a clock input of the counter.
10. The timer circuit of claim 1 wherein:
when a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired, a first portion of the frequency indication is provided to the load input of the one counter; and
the one counter is selected from the plurality of counters based upon a second portion of the frequency indication.
11. The timer circuit of claim 10 wherein the first portion of the frequency indication indicates a numerical value of the frequency of the clock signal and the second portion of the frequency indication indicates a frequency unit of the clock signal.
12. A timer circuit, comprising:
a delay indication circuit, the delay indication circuit providing a delay time indication;
a frequency indication circuit, the frequency indication circuit providing a frequency indication of a frequency of a clock signal;
a clock input to receive the clock signal; and
a plurality of counters, wherein each counter of the plurality of counters includes a load input to receive an initial value and an indication output to provide a count complete indication of the counter, wherein during operation when a set of the counters of the plurality of counters is coupled in series to provide an indication that a delay time has expired, at least a portion of the frequency indication is provided to the load input of one counter of the set and at least a portion of the delay time indication is provided to the load input of another counter of the set, and wherein each counter of the plurality of counters includes a clock input for receiving the clock signal.
13. A method comprising:
providing a delay time indication to a counter circuit, the delay time indication indicating a desired delay time to be indicated by the counter circuit;
providing a frequency indication to the counter circuit;
providing a clock signal to the counter circuit, the frequency indication indicating the frequency of the clock signal; and
running a set of a plurality of counters of the counter circuit coupled in series and using an output of the set to provide an indication of an expired delay time, wherein each counter of the set includes an indication output to provide a count complete indication of the counter, wherein during the running, the indication output of each preceding counter of the set is coupled to an input of a subsequent counter of the set, wherein prior to the running, at least a portion of the frequency indication is loaded into one counter of the set and at least a portion of the delay time indication is loaded into another counter of the set.
14. The method of claim 13 further wherein:
the delay time indication includes a first portion and a second portion, wherein the first portion is loaded into the another counter;
wherein the second portion is used to select the another counter from a plurality of counters of the counter circuit.
15. The method of claim 13 wherein the using the output of the set to provide an indication of an expired delay time includes using the indication output of the another counter to provide the indication of the expired delay time.
16. The method of claim 13 further wherein:
the one counter of the set is the initial in series counter of the set.
17. The method of claim 16 wherein:
the frequency indication includes a first portion and a second portion, wherein the first portion is loaded into the one counter;
wherein the second portion is used to select the one counter from a plurality of counters of the counter circuit.
18. The method of claim 13 wherein the set includes an intermediate counter coupled between the one counter and the another counter in the series, wherein the indication output of the intermediate counter is coupled to an input of the another counter in the set, wherein prior to the running, a predetermined value is loaded into the intermediate counter.
19. A method comprising:
providing a delay time indication to a counter circuit including a plurality of counters, the delay time indication including a first portion and a second portion, the delay time indication indicating a desired delay time to be indicated by the counter circuit, wherein each counter of the plurality of counters includes an indication output to provide a count complete indication of the counter;
providing a frequency indication to the counter circuit;
providing a clock signal to the counter circuit, the frequency indication indicating the frequency of the clock signal;
coupling a set of the plurality of counters in series, wherein the indication output of each preceding counter of the set is coupled to an input of a subsequent counter of the set, wherein the coupling includes selecting a selected counter of the plurality of counters based on the second portion of the delay time indication, the set including the selected counter, wherein the coupling includes selecting an initial in series counter for the set from the plurality of counters;
loading the initial in series counter with at least a portion of the frequency indication;
loading the selected counter with the first portion of the delay time indication; and
after the loading the initial in series counter and the selected counter, running the counters of the set and using the indication output of the selected counter to provide an indication of an expired delay time.
20. The method of claim 19 wherein:
the loading the initial in series counter includes loading the initial in series counter with a first portion of the frequency indication; and
the selecting the initial in series counter for the set from the plurality of counters includes selecting based on a second portion of the frequency indication.