IP Library Granted Patent US 8,592,894
Granted Patent B2
US 8,592,894 · App. 12/999,143 · Granted Nov 26, 2013

Method of forming a power semiconductor device and power semiconductor device

Inventors: Jean Michel Reynes (Pompertuzat, FR); Evgueniy Stafanov (Vieille Toulouse, FR); Yann Weber (Toulouse, FR)
Assignee: Freescale Semiconductor, Inc.
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Quick Facts
Patent No.
US 8,592,894
App. No.
12/999,143
Granted
Nov 26, 2013
Kind
B2
Abstract

A method of forming a power semiconductor device comprises forming a first semiconductor layer of a first conductivity type extending across the power semiconductor device; forming an epitaxial layer of the first conductivity type over the first semiconductor layer, the epitaxial layer having a doping concentration that increases from a first surface of the epitaxial layer towards the first semiconductor layer; forming a body region of a second conductivity type in the epitaxial layer extending from the first surface of the epitaxial layer into the epitaxial layer, wherein a junction between the body region and the epitaxial layer is at or substantially adjacent to a region of the epitaxial layer having a maximum doping concentration; and forming a gate region such that the gate region is adjacent at least a portion of the body region. In operation of the semiconductor device, the portion of the body region adjacent the gate region functions as a channel region of the semiconductor device.

Claims (32)

1. A method of forming a power semiconductor device comprising:

forming a first semiconductor layer of a first conductivity type extending across the power semiconductor device;

forming an epitaxial layer of the first conductivity type over the first semiconductor layer, the epitaxial layer having a doping concentration that increases from a first surface of the epitaxial layer towards the first semiconductor layer to provide a first region adjacent to the first surface having a doping concentration lower than a second region adjacent to the first semiconductor layer;

forming a body region of a second conductivity type in the epitaxial layer extending from the first surface of the epitaxial layer into the epitaxial layer, wherein a PN junction between the body region and the epitaxial layer extends through the first region and into the second region so that a maximum depth of the PN junction is at or just adjacent to a region of the epitaxial layer having a maximum doping concentration; and

forming a gate region such that the gate region is adjacent at least a portion of the body region, wherein in operation of the semiconductor device the portion of the body region adjacent the gate region functions as a channel region of the semiconductor device.

2. The method according to claim 1 , wherein forming an epitaxial layer comprises forming a blanket epitaxial layer extending across substantially all of the first semiconductor layer.

3. The method according to claim 1 , wherein the first semiconductor layer is an epitaxial layer and wherein the steps of forming the first semiconductor layer and the epitaxial layer are performed in the same epitaxial apparatus.

4. The method according to claim 1 , wherein the first semiconductor layer has a first doping concentration of the first conductivity type and wherein the doping concentration across the epitaxial layer is greater than the first doping concentration.

5. The method according to claim 1 , wherein the step of forming the gate region comprises forming the gate region over the first surface of the epitaxial layer such that the gate region extends over at least a portion of the body region and at least a portion of the epitaxial layer.

6. The method according to claim 1 , further comprising forming a current electrode region of the first conductivity type in the body region extending from the first surface into the body region.

7. The method according to claim 1 , wherein forming a first semiconductor layer comprises forming the first semiconductor layer over a semiconductor substrate.

8. The method according to claim 7 , wherein the semiconductor substrate is of the second conductivity type and has a first surface and a second surface wherein the first semiconductor layer is formed over the first surface of the semiconductor substrate and wherein the method further comprises forming a current electrode over the second surface of the semiconductor substrate.

9. The method according to claim 1 , wherein the power semiconductor device comprises an active area and a termination area surrounding the active area, wherein the first semiconductor layer, and the epitaxial layer extend across the active area and termination area and wherein the body region and gate region are formed in the active area, the method further comprising forming at least one protection structure in the termination area to compensate for the doping concentration of the epitaxial layer.

10. The method according to claim 9 , wherein the protection structure comprises at least one of:

a termination region of the second conductivity type in the termination area, the at least one termination region extending from the first surface of the epitaxial layer into the epitaxial layer and

a termination region of the first conductivity type in the epitaxial layer adjacent the first surface of the epitaxial layer.

11. A power semiconductor device comprising:

a first semiconductor layer of a first conductivity type extending across the power semiconductor device;

an epitaxial layer of the first conductivity type formed over the first semiconductor layer, the epitaxial layer having a doping concentration that increases from a first surface of the epitaxial layer towards the first semiconductor layer to provide a first region adjacent to the first surface having a doping concentration lower than a second region adjacent to the first semiconductor layer;

a body region of a second conductivity type formed in the epitaxial layer extending from the first surface of the epitaxial layer into the epitaxial layer, wherein a PN junction between the body region and the epitaxial layer extends through the first region and into the second region so that a maximum depth of the PN junction is at or just adjacent to a region of the epitaxial layer having a maximum doping concentration; and

a gate region adjacent at least a portion of the body region, wherein in operation of the semiconductor device the portion of the body region adjacent the gate region functions as a channel region of the semiconductor device.

12. The power semiconductor device according to claim 11 , wherein the epitaxial layer is a blanket epitaxial layer extending across substantially all of the first semiconductor layer.

13. The power semiconductor device according to claim 11 , wherein the first semiconductor layer has a first doping concentration of the first conductivity type and wherein the doping concentration across the epitaxial layer is greater than the first doping concentration.

14. The power semiconductor device according to claim 11 , wherein the gate region is formed over the first surface of the epitaxial layer such that the gate region extends over at least a portion of the body region and at least a portion of the epitaxial layer.

15. The power semiconductor device according to claim 11 , further comprising a current electrode region of the first conductivity type formed in the body region extending from the first surface into the body region.

16. The power semiconductor device according to claim 11 , further comprising a semiconductor substrate, wherein the first semiconductor layer is formed over the semiconductor substrate.

17. The power semiconductor device according to claim 16 , wherein the semiconductor substrate is of the second conductivity type and has a first surface and a second surface wherein the first semiconductor layer is formed over the first surface of the semiconductor substrate and the semiconductor device further comprises a current electrode formed over the second surface of the semiconductor substrate.

18. The power semiconductor device according to claim 11 , wherein the power semiconductor device comprises an active area and a termination area surrounding the active area, wherein the first semiconductor layer, and the epitaxial layer extend across the active area and termination area and wherein the body region and gate region are formed in the active area, the semiconductor device further comprising at least one protection structure formed in the termination area to compensate for the doping concentration of the epitaxial layer.

19. The power semiconductor device according to claim 18 , wherein the protection structure comprises at least one of:

a termination region of the second conductivity type in the termination area, the at least one termination region extending from the first surface of the epitaxial layer into the epitaxial layer; and

a termination region of the first conductivity type in the epitaxial layer adjacent the first surface of the epitaxial layer.

20. The method according to claim 1 wherein the first region and the second region of the epitaxial layer are formed during one epitaxial process, and wherein a concentration of a dopant of the first type is varied during the epitaxial process.

Assignments (31)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0387 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0285 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0334 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0477 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027621/0928 →
SECURITY AGREEMENT Recorded Jan 31, 2012
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027622/0075 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2010
From: REYNES, JEAN MICHEL; STEFANOV, EVGUENIY; WEBER, YANN
To: FREESCALE SEMICONDUCTOR INC.
Reel/Frame 025504/0415 →
Continuity (1)
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