Result forwarding to dependent instruction in pipelined processor with mode selectable execution in E1 or E2 of pipelined operational stages
View Patent ↗A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.
1. A system, comprising:
a processor comprising a pipeline, wherein the pipeline comprises:
a plurality of pipeline stages, wherein the plurality of pipeline stages comprise a prior pipeline stage and a subsequent pipeline stage, wherein the prior pipeline stage performs a first set of computational operations if a first data-dependent instruction is being executed and a first mode has been selected, and wherein the subsequent pipeline stage performs the first set of computational operations if the first data-dependent instruction is being executed and a second mode has been selected;
feedforward logic capable of providing computational results obtained from execution of a previous instruction by the subsequent pipeline stage to the prior pipeline stage for use during execution of the first data-dependent instruction; and
feedforward control circuitry which selects a first set of feedforward control values to provide to the feedforward logic during execution of the first data-dependent instruction if the first mode has been selected, and which selects a second set of feedforward control values to provide to the feedforward logic during execution of the first data-dependent instruction if the second mode has been selected, wherein the first set of feedforward control values and the second set of feedforward control values are different.
2. A system as in claim 1 , wherein if the first mode has been selected and execution of the first set of computational operations occurs in the prior pipeline stage, the first data-dependent instruction has a first latency, and wherein if the second mode has been selected and execution of the first set of computational operations occurs in the subsequent pipeline stage, the first data-dependent instruction still has the first latency.
3. A system as in claim 1 , wherein the first set of computational operations comprises an integer operation.
4. A system as in claim 1 , further comprising:
a memory having a plurality of modes, wherein the plurality of modes comprise the first mode and the second mode.
5. A system as in claim 1 , wherein the first mode comprises a parity protected mode.
6. A system as in claim 1 , wherein the second mode comprises an error correction code (ECC) protected mode.
7. A system as in claim 1 , wherein the data processor performs a second set of computational operations during execution of a second data-dependent instruction, and wherein both the prior pipeline stage and the subsequent pipeline stage are used when performing the second set of computational operations during execution of the second data-dependent instruction regardless of whether the first mode or the second mode is selected.